ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
{
struct spi_slave *slave;
u8 cmd = SPI_EEPROM_READ;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave)
return 0;
spi_claim_bus(slave);
/* command */
if (spi_xfer(slave, 8, &cmd, NULL, SPI_XFER_BEGIN))
return -1;
/*
* if alen == 3, addr[0] is the block number, we never use it here.
* All we need are the lower 16 bits.
*/
if (alen == 3)
addr++;
/* address, and data */
if (spi_xfer(slave, 16, addr, NULL, 0))
return -1;
if (spi_xfer(slave, 8 * len, NULL, buffer, SPI_XFER_END))
return -1;
spi_release_bus(slave);
spi_free_slave(slave);
return len;
}
static struct spi_slave *enbw_cmc_init_spi(void)
{
struct spi_slave *spi;
int ret;
spi = spi_setup_slave(0, 0, 1000000, 0);
if (!spi) {
printf("Failed to set up slave\n");
return NULL;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("Failed to claim SPI bus: %d\n", ret);
goto err_claim_bus;
}
ret = enbw_cmc_switch_read_ident(spi);
if (ret)
goto err_read;
return spi;
err_read:
spi_release_bus(spi);
err_claim_bus:
spi_free_slave(spi);
return NULL;
}
int cros_ec_spi_packet(struct udevice *udev, int out_bytes, int in_bytes)
{
struct cros_ec_dev *dev = dev_get_uclass_priv(udev);
struct spi_slave *slave = dev_get_parentdata(dev->dev);
int rv;
/* Do the transfer */
if (spi_claim_bus(slave)) {
debug("%s: Cannot claim SPI bus\n", __func__);
return -1;
}
rv = spi_xfer(slave, max(out_bytes, in_bytes) * 8,
dev->dout, dev->din,
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
if (rv) {
debug("%s: Cannot complete SPI transfer\n", __func__);
return -1;
}
return in_bytes;
}
int lg4573_spi_startup(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
debug("%s: Failed to set up slave\n", __func__);
return -1;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
goto err_claim_bus;
}
lb043wv_display_mode_settings(spi);
lb043wv_power_settings(spi);
lb043wv_gamma_settings(spi);
lb043wv_display_on(spi);
return 0;
err_claim_bus:
spi_free_slave(spi);
return -1;
}
void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
{
struct spi_flash *flash;
spi_init();
flash = spi_flash_probe(0, 0);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
/* Dont make flow stop. */
return;
}
flash->spi->rw = SPI_WRITE_FLAG;
spi_claim_bus(flash->spi);
flash->erase(flash, pos, size);
flash->write(flash, pos, sizeof(len), &len);
u32 nvram_pos;
for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
}
flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos));
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
return;
}
static int lq035q1_control(unsigned char reg, unsigned short value)
{
int ret;
u8 regs[3] = {LQ035_INDEX, 0, 0};
u8 data[3] = {LQ035_DATA, 0, 0};
u8 dummy[3];
regs[2] = reg;
data[1] = value >> 8;
data[2] = value & 0xFF;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
CONFIG_LQ035Q1_SPI_CS, 20000000,
SPI_MODE_3);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return ret;
}
int rtc_set(struct rtc_time *rtc)
{
u32 time, day, reg;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
if (spi_claim_bus(slave))
return -1;
reg = 0x2c000000 | day | 0x80000000;
spi_xfer(slave, 32, (uchar *)®, (uchar *)&day,
SPI_XFER_BEGIN | SPI_XFER_END);
reg = 0x28000000 | time | 0x80000000;
spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return -1;
}
/* set clock time from *tmp in DS1306 RTC */
void rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
spi_release_bus(slave);
}
/* Test that sandbox SPI works correctly */
static int dm_test_spi_xfer(struct dm_test_state *dms)
{
struct spi_slave *slave;
struct udevice *bus;
const int busnum = 0, cs = 0, mode = 0;
const char dout[5] = {0x9f};
unsigned char din[5];
ut_assertok(spi_get_bus_and_cs(busnum, cs, 1000000, mode, NULL, 0,
&bus, &slave));
ut_assertok(spi_claim_bus(slave));
ut_assertok(spi_xfer(slave, 40, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END));
ut_asserteq(0xff, din[0]);
ut_asserteq(0x20, din[1]);
ut_asserteq(0x20, din[2]);
ut_asserteq(0x15, din[3]);
spi_release_bus(slave);
/*
* Since we are about to destroy all devices, we must tell sandbox
* to forget the emulation device
*/
#ifdef CONFIG_DM_SPI_FLASH
sandbox_sf_unbind_emul(state_get_current(), busnum, cs);
#endif
return 0;
}
/* reset the DS1306 */
void rtc_reset (void)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
/* clear the control register */
rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
/* reset all alarms */
rtc_write (RTC_SECONDS_ALARM0, 0x00);
rtc_write (RTC_SECONDS_ALARM1, 0x00);
rtc_write (RTC_MINUTES_ALARM0, 0x00);
rtc_write (RTC_MINUTES_ALARM1, 0x00);
rtc_write (RTC_HOURS_ALARM0, 0x00);
rtc_write (RTC_HOURS_ALARM1, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
spi_release_bus(slave);
}
static int sx151x_spi_read(int chip, unsigned char reg)
{
struct spi_slave *slave;
int ret;
slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
SPI_MODE_0);
if (!slave)
return 0;
spi_claim_bus(slave);
ret = spi_w8r8(slave, reg | 0x80);
if (ret < 0)
printf("spi%d.%d read fail: can't read %02x: %d\n",
CONFIG_SX151X_SPI_BUS, chip, reg, ret);
else
printf("spi%d.%d read register 0x%02x: 0x%02x\n",
CONFIG_SX151X_SPI_BUS, chip, reg, ret);
spi_release_bus(slave);
spi_free_slave(slave);
return ret;
}
static int sx151x_spi_write(int chip, unsigned char reg, unsigned char val)
{
struct spi_slave *slave;
unsigned char buf[2];
int ret;
slave = spi_setup_slave(CONFIG_SX151X_SPI_BUS, chip, 1000000,
SPI_MODE_0);
if (!slave)
return 0;
spi_claim_bus(slave);
buf[0] = reg;
buf[1] = val;
ret = spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
if (ret < 0)
printf("spi%d.%d write fail: can't write %02x to %02x: %d\n",
CONFIG_SX151X_SPI_BUS, chip, val, reg, ret);
else
printf("spi%d.%d write 0x%02x to register 0x%02x\n",
CONFIG_SX151X_SPI_BUS, chip, val, reg);
spi_release_bus(slave);
spi_free_slave(slave);
return ret;
}
int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
{
unsigned long page_addr, byte_addr, page_size;
size_t chunk_len, actual;
int ret;
u8 cmd[5];
page_size = flash->page_size;
page_addr = offset / page_size;
byte_addr = offset % page_size;
ret = spi_claim_bus(flash->spi);
if (ret) {
debug("SF: unable to claim SPI bus\n");
return ret;
}
cmd[0] = CMD_PAGE_PROGRAM;
for (actual = 0; actual < len; actual += chunk_len) {
chunk_len = min(len - actual, page_size - byte_addr);
if (ADDR_WIDTH(flash->size) == 4) {
cmd[1] = page_addr >> 16;
cmd[2] = page_addr >> 8;
cmd[3] = page_addr;
cmd[4] = byte_addr;
debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } "
"chunk_len = %zu\n", buf + actual, cmd[0],
cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);
} else {
static int do_spi_xfer(int bus, int cs)
{
struct spi_slave *slave;
int rcode = 0;
slave = spi_setup_slave(bus, cs, 1000000, mode);
if (!slave) {
printf("Invalid device %d:%d\n", bus, cs);
return -EINVAL;
}
spi_claim_bus(slave);
if (spi_xfer(slave, bitlen, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END) != 0) {
printf("Error during SPI transaction\n");
rcode = -EIO;
} else {
int j;
for (j = 0; j < ((bitlen + 7) / 8); j++)
printf("%02X", din[j]);
printf("\n");
}
spi_release_bus(slave);
spi_free_slave(slave);
return rcode;
}
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
* @flashp: Pointer to place to put flash info, which may be NULL if the
* space should be allocated
*/
static int spi_flash_probe_slave(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
int ret;
/* Setup spi_slave */
if (!spi) {
printf("SF: Failed to set up slave\n");
return -ENODEV;
}
/* Claim spi bus */
ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Failed to claim SPI bus: %d\n", ret);
return ret;
}
ret = spi_nor_scan(flash);
if (ret)
goto err_read_id;
#ifdef CONFIG_SPI_FLASH_MTD
ret = spi_flash_mtd_register(flash);
#endif
err_read_id:
spi_release_bus(spi);
return ret;
}
void work_92105_display_init(void)
{
int claim_err;
char *display_contrast_str;
uint8_t display_contrast = CONTRAST_DEFAULT;
uint8_t enable_backlight = 0x96;
slave = spi_setup_slave(0, 0, 500000, 0);
if (!slave) {
printf("Failed to set up SPI slave\n");
return;
}
claim_err = spi_claim_bus(slave);
if (claim_err)
debug("Failed to claim SPI bus: %d\n", claim_err);
/* enable backlight */
i2c_write(0x2c, 0x01, 1, &enable_backlight, 1);
/* set display contrast */
display_contrast_str = getenv("fwopt_dispcontrast");
if (display_contrast_str)
display_contrast = simple_strtoul(display_contrast_str,
NULL, 10);
i2c_write(0x2c, 0x00, 1, &display_contrast, 1);
/* request GPO_15 as an output initially set to 1 */
gpio_request(GPO_15, "MAX6957_nCS");
gpio_direction_output(GPO_15, 1);
/* enable MAX6957 portexpander */
max6957aax_write(MAX6957_CONF, 0x01);
/* configure pin 8 as input, pins 9..19 as outputs */
max6957aax_write(MAX6957_CONF_08_11, 0x56);
max6957aax_write(MAX6957_CONF_12_15, 0x55);
max6957aax_write(MAX6957_CONF_16_19, 0x55);
/* initialize HD44780 */
max6957aax_write(MAX6957AAX_HD44780_EN, 0);
hd44780_instruction(HD44780_FUNCTION_SET);
hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL);
hd44780_instruction(HD44780_ENTRY_MODE_SET);
/* write custom character glyphs */
hd44780_init_char_gen();
/* Show U-Boot version, date and time as a sign-of-life */
hd44780_instruction(HD44780_CLEAR_DISPLAY);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0);
hd44780_write_str(U_BOOT_VERSION);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64);
hd44780_write_str(U_BOOT_DATE);
hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20);
hd44780_write_str(U_BOOT_TIME);
}
u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
{
u32 pos;
struct spi_flash *flash;
u8 *new_data;
u32 bytes_to_process;
u32 nvram_pos;
if (S3DataType == S3DataTypeNonVolatile)
pos = S3_DATA_NONVOLATILE_POS;
else
pos = S3_DATA_VOLATILE_POS;
spi_init();
flash = spi_flash_probe(0, 0, 0, 0);
if (!flash) {
printk(BIOS_DEBUG, "%s: Could not find SPI device\n", __func__);
/* Don't make flow stop. */
return AGESA_SUCCESS;
}
flash->spi->rw = SPI_WRITE_FLAG;
spi_claim_bus(flash->spi);
// initialize the incoming data array
new_data = (u8 *)malloc(DataSize + (u32)sizeof(DataSize));
memcpy(new_data, &DataSize, (u32)sizeof(DataSize)); // the size gets written first
memcpy(new_data + (u32)sizeof(DataSize), Data, DataSize);
DataSize += (u32)sizeof(DataSize); // add in the size of the data
for ( ; DataSize > 0; DataSize -= bytes_to_process) {
bytes_to_process = ( DataSize >= flash->sector_size) ? flash->sector_size : DataSize;
if (memcmp((u8 *)pos, (u8 *)new_data, bytes_to_process)) {
printk(BIOS_DEBUG, "%s: Data mismatch - write the data\n", __func__);
flash->erase(flash, pos, flash->sector_size);
for (nvram_pos = 0; \
nvram_pos < bytes_to_process - (bytes_to_process % CONFIG_AMD_SB_SPI_TX_LEN); \
nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
flash->write(flash, pos + nvram_pos, CONFIG_AMD_SB_SPI_TX_LEN, \
(u8 *)(new_data + nvram_pos));
}
flash->write(flash, pos + nvram_pos, bytes_to_process % CONFIG_AMD_SB_SPI_TX_LEN, \
(u8 *)(new_data + nvram_pos));
}
else
printk(BIOS_DEBUG, "%s: existing nvram data matched\n", __func__);
new_data += bytes_to_process;
pos += bytes_to_process;
}
free(new_data);
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
return AGESA_SUCCESS;
}
int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
{
int ret;
spi_claim_bus(spi);
ret = spi_aml_cmd(spi, &cmd, len*8, NULL,response, 0);
spi_release_bus(spi);
return ret;
}
static int mmc_spi_init_p(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
spi_claim_bus(spi);
/* cs deactivated for 100+ clock */
spi_xfer(spi, 18 * 8, NULL, NULL, 0);
spi_release_bus(spi);
return 0;
}
static int crosec_spi_io(size_t req_size, size_t resp_size, void *context)
{
struct spi_slave *slave = (struct spi_slave *)context;
int ret = 0;
/* Wait minimum delay between CS assertions. */
stopwatch_wait_until_expired(&cs_cooldown_sw);
spi_claim_bus(slave);
/* Allow EC to ramp up clock after being awaken.
* See chrome-os-partner:32223 for more details. */
udelay(CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US);
if (spi_xfer(slave, req_buf, req_size, NULL, 0)) {
printk(BIOS_ERR, "%s: Failed to send request.\n", __func__);
ret = -1;
goto out;
}
uint8_t byte;
struct stopwatch sw;
// Wait 1s for a framing byte.
stopwatch_init_usecs_expire(&sw, USECS_PER_SEC);
while (1) {
if (spi_xfer(slave, NULL, 0, &byte, sizeof(byte))) {
printk(BIOS_ERR, "%s: Failed to receive byte.\n",
__func__);
ret = -1;
goto out;
}
if (byte == EcFramingByte)
break;
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR,
"%s: Timeout waiting for framing byte.\n",
__func__);
ret = -1;
goto out;
}
}
if (spi_xfer(slave, NULL, 0, resp_buf, resp_size)) {
printk(BIOS_ERR, "%s: Failed to receive response.\n", __func__);
ret = -1;
}
out:
spi_release_bus(slave);
stopwatch_init_usecs_expire(&cs_cooldown_sw, cs_cooldown_us);
return ret;
}
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len)
{
struct spi_slave *spi = flash->spi;
int ret;
spi_claim_bus(spi);
ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
spi_release_bus(spi);
return ret;
}
int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
const void *data, size_t data_len)
{
int ret;
spi_claim_bus(spi);
ret = spi_aml_cmd(spi, cmd, data_len, data,NULL, SPI_CMD_HAS_ADDR);
spi_release_bus(spi);
return ret;
}
int spi_flash_read_aml(struct spi_flash *flash,u32 offset, size_t len, void *buf){
struct spi_slave *spi = flash->spi;
//int ret;
u32 temp_addr;
int temp_length;
temp_addr = offset;
temp_length = len;
unsigned flags;
/* 0x400000 ~ 0x7fffff */
if(temp_addr + len > 0x400000 && temp_addr < 0x400000){
flags=SPI_XFER_END|SPI_XFER_COPY;
spi_xfer(spi,(0x400000-temp_addr)*8,&temp_addr,buf,flags);
buf += (0x400000-temp_addr);
temp_length = len - (0x400000-temp_addr);
temp_addr = 0x400000;
}
/* 0x000000 ~ 0x3fffff */
else if(temp_addr < 0x400000){
flags=SPI_XFER_END|SPI_XFER_COPY;
spi_xfer(spi,temp_length*8,&temp_addr,buf,flags);
return 0;
}
spi_claim_bus(spi); /*FIXME for spi_xfer release bus*/
while(temp_length>0){
flags=(temp_addr & 0xffffff)|( (temp_length>=32?32:temp_length) << SPI_FLASH_BYTES_LEN);
spi_flash_adr_write(spi, flags);
flags=(1<<SPI_FLASH_READ);
spi_flash_cmd(spi,flags,NULL,0);
flags=SPI_XFER_READCACHE;
spi_xfer(spi,(temp_length>=32?32:temp_length)*8,NULL,buf,flags);
temp_addr += (temp_length>=32?32:temp_length);
buf += (temp_length>=32?32:temp_length);
temp_length -= (temp_length>=32?32:temp_length);
}
return 0;
}
static void
amoled_write_spi_command(struct spi_slave *spi, unsigned char command, unsigned char arg)
{
unsigned char spi_cmd[2];
spi_cmd[0] = command;
spi_cmd[1] = arg;
/* SPI_MODE_1 (clk active high) */
spi_claim_bus(spi);
spi_xfer(spi, 8*2, spi_cmd, NULL, 0);
spi_release_bus(spi);
}
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
u32 reg;
int err, tim, i = 0;
if (!slave) {
/* FIXME: Verify the max SCK rate */
slave = spi_setup_slave(CONFIG_MC13783_SPI_BUS,
CONFIG_MC13783_SPI_CS, 1000000,
SPI_MODE_2 | SPI_CS_HIGH);
if (!slave)
return -1;
}
if (spi_claim_bus(slave))
return -1;
do {
reg = 0x2c000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day1,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x28000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&time,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
reg = 0x2c000000;
err = spi_xfer(slave, 32, (uchar *)®, (uchar *)&day2,
SPI_XFER_BEGIN | SPI_XFER_END);
if (err)
return err;
} while (day1 != day2 && i++ < 3);
spi_release_bus(slave);
tim = day1 * 86400 + time;
to_tm(tim, rtc);
rtc->tm_yday = 0;
rtc->tm_isdst = 0;
return 0;
}
ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
{
struct spi_slave *slave;
char buf[3];
ulong start;
slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, 1, 1000000,
CONFIG_DEFAULT_SPI_MODE);
if (!slave)
return 0;
spi_claim_bus(slave);
buf[0] = SPI_EEPROM_WREN;
if (spi_xfer(slave, 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END))
return -1;
buf[0] = SPI_EEPROM_WRITE;
/* As for reading, drop addr[0] if alen is 3 */
if (alen == 3) {
alen--;
addr++;
}
memcpy(buf + 1, addr, alen);
/* command + addr, then data */
if (spi_xfer(slave, 24, buf, NULL, SPI_XFER_BEGIN))
return -1;
if (spi_xfer(slave, len * 8, buffer, NULL, SPI_XFER_END))
return -1;
start = get_timer(0);
do {
buf[0] = SPI_EEPROM_RDSR;
buf[1] = 0;
spi_xfer(slave, 16, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
if (!(buf[1] & 1))
break;
} while (get_timer(start) < CONFIG_SYS_SPI_WRITE_TOUT);
if (buf[1] & 1)
printf("*** spi_write: Timeout while writing!\n");
spi_release_bus(slave);
spi_free_slave(slave);
return len;
}
/* control backlight pwm (display brightness).
* allow values 0-250 with 0 = turn off and 250 = max brightness
*/
void mergerbox_tft_dim(u16 value)
{
struct spi_slave *slave;
u16 din;
u16 dout = 0;
if (value > 0 && value < 250)
dout = 0x4000 | value;
slave = spi_setup_slave(0, 0, 1000000, SPI_MODE_0 | SPI_CS_HIGH);
spi_claim_bus(slave);
spi_xfer(slave, 16, &dout, &din, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
spi_free_slave(slave);
}
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
* @flashp: Pointer to place to put flash info, which may be NULL if the
* space should be allocated
*/
static int spi_flash_probe_slave(struct spi_flash *flash)
{
struct spi_slave *spi = flash->spi;
u8 mode_rx, e_rd_cmd;
int ret;
/* Setup spi_slave */
if (!spi) {
printf("SF: Failed to set up slave\n");
return -ENODEV;
}
/* Convert SPI mode_rx and mode to SPI flash read commands */
mode_rx = spi->mode_rx;
if (mode_rx & SPI_RX_QUAD) {
e_rd_cmd = RD_NORM | QUAD_OUTPUT_FAST;
if (spi->mode & SPI_TX_QUAD)
e_rd_cmd |= QUAD_IO_FAST;
} else if (mode_rx & SPI_RX_DUAL) {
e_rd_cmd = RD_NORM | DUAL_OUTPUT_FAST;
if (spi->mode & SPI_TX_DUAL)
e_rd_cmd |= DUAL_IO_FAST;
} else if ((mode_rx & (SPI_RX_SLOW | SPI_RX_FAST)) == SPI_RX_SLOW) {
e_rd_cmd = ARRAY_SLOW;
} else {
e_rd_cmd = RD_NORM;
}
/* Claim spi bus */
ret = spi_claim_bus(spi);
if (ret) {
debug("SF: Failed to claim SPI bus: %d\n", ret);
return ret;
}
ret = spi_flash_scan(flash, e_rd_cmd);
if (ret)
goto err_read_id;
#ifdef CONFIG_SPI_FLASH_MTD
ret = spi_flash_mtd_register(flash);
#endif
err_read_id:
spi_release_bus(spi);
return ret;
}
void OemAgesaSaveMtrr(void)
{
#ifndef __PRE_RAM__
msr_t msr_data;
u32 nvram_pos = S3_DATA_MTRR_POS;
u32 i;
struct spi_flash *flash;
if (!check_saved_mtrr_data(nvram_pos))
return;
spi_init();
flash = spi_flash_probe(0, 0, 0, 0);
if (!flash) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}
flash->spi->rw = SPI_WRITE_FLAG;
spi_claim_bus(flash->spi);
flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE);
/* Enable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Fixed MTRRs */
for (i = 0; i < (u32)sizeof(mtrr_table_fixed_MTRR)/sizeof(u32); i++)
write_mtrr(flash, &nvram_pos, mtrr_table_fixed_MTRR[i]);
/* Disable access to AMD RdDram and WrDram extension bits */
msr_data = rdmsr(SYS_CFG);
msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
wrmsr(SYS_CFG, msr_data);
/* Variable MTRRs, SYS_CFG, TOM, TOM2 */
for (i = 0; i < (u32)sizeof(mtrr_table_var_MTRR)/sizeof(u32); i++)
write_mtrr(flash, &nvram_pos, mtrr_table_var_MTRR[i]);
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
#endif
}
static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
{
u32 pmic_tx, pmic_rx;
u32 tmp;
if (!slave) {
slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk,
p->hw.spi.mode);
if (!slave)
return -ENODEV;
}
if (check_reg(p, reg))
return -EINVAL;
if (spi_claim_bus(slave))
return -EBUSY;
pmic_tx = p->hw.spi.prepare_tx(reg, val, write);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
pmic_spi_flags))
goto err;
if (write) {
pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
pmic_spi_flags))
goto err;
}
spi_release_bus(slave);
*val = cpu_to_be32(pmic_rx);
return 0;
err:
spi_release_bus(slave);
return -ENOTSUPP;
}
