// setup screen and pad void interface_setup() { // SPI gpio_mode_setup(INTERFACE_SPI_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, INTERFACE_SPI_CLK_PIN | INTERFACE_SPI_MISO_PIN | INTERFACE_SPI_MOSI_PIN ); gpio_set_af(INTERFACE_SPI_PORT, GPIO_AF5, INTERFACE_SPI_CLK_PIN | INTERFACE_SPI_MISO_PIN | INTERFACE_SPI_MOSI_PIN); gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1); gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4 | GPIO5); rcc_periph_clock_enable(RCC_SPI1); spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); spi_enable(SPI1); // OLED ssd1306_setup(); // PAD pad_setup(); nvic_set_priority(NVIC_EXTI0_IRQ,0x00); /* Enable EXTI0 interrupt. */ nvic_enable_irq(NVIC_EXTI0_IRQ); gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, GPIO0); /* Configure the EXTI subsystem. */ exti_select_source(EXTI0, GPIOA); exti_set_trigger(EXTI0, EXTI_TRIGGER_FALLING); exti_enable_request(EXTI0); }
/** Set up the SPI buses. * Set up the SPI peripheral, SPI clocks, SPI pins, and SPI pins' clocks. */ void spi_setup(void) { /* Enable SPI1 periperal clock */ RCC_APB2ENR |= RCC_APB2ENR_SPI1EN; /* Enable SPI2 periperal clock */ RCC_APB1ENR |= RCC_APB1ENR_SPI2EN; /* Enable GPIO clocks for CS lines */ RCC_AHB1ENR |= RCC_AHB1ENR_IOPAEN | RCC_AHB1ENR_IOPBEN; /* Setup CS line GPIOs */ /* Deselect FPGA CS */ gpio_set(GPIOA, GPIO4); /* Deselect configuration flash and front-end CS */ gpio_set(GPIOB, GPIO11 | GPIO12); /* FPGA CS */ gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO4); /* Configuration flash CS */ gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO12); /* Front-end CS */ gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO11); /* Setup SPI alternate function */ gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7); gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7); gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 | GPIO15); gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15); /* Setup SPI parameters. */ spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); /* Required, see 25.3.1 section about NSS */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); /* Required, see 25.3.1 section about NSS */ /* Finally enable the SPI. */ spi_enable(SPI1); spi_enable(SPI2); chMtxInit(&spi_mutex); }
/* *************** HAL API functions **************************************** */ void hal_init( void ) { int ret = 0; /* Reset variables used in file. */ hal_system_time = 0; // hal_reset_flags(); /* Enable GPIOA clock. Enable AFIO clock. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN ); /* The following pins are output pins. */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, SCK | MOSI | MISO); //sck mosi miso spi_disable(RF_SPI); SPI2_I2SCFGR = 0; /* Setup SPI parameters. */ spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_set_unidirectional_mode(RF_SPI); spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */ spi_enable_software_slave_management(RF_SPI); spi_set_nss_high(RF_SPI); spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */ /* Finally enable the SPI. */ spi_enable(RF_SPI); /* Set GPIO4 (in GPIO port C) to 'input float'. */ gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN); gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN); /* Configure the EXTI subsystem. */ exti_select_source(EXTI4, RF_IRQ_PORT); exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING); exti_enable_request(EXTI4); exti_reset_request(EXTI4); PRINTF("Enabling interrupts\r\n"); /* Enable EXTI0 interrupt. */ nvic_enable_irq(NVIC_EXTI4_IRQ); nvic_set_priority(NVIC_EXTI4_IRQ,4); //@@@!? timer_init(); // ret = trx_init(); // if(ret!=0) // { // PRINTF("rf231:hal init failed\r\n"); // }else // { // PRINTF("rf231:hal init success\r\n"); // } }
static void spi_setup(void) { gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 | GPIO15); gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15); /* Setup SPI parameters. */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); /* Required, see NSS, 25.3.1 section. */ /* Finally enable the SPI. */ spi_enable(SPI2); }
void spi_start(void) { /* Reset flash chip */ gpio_clear(GPIOD, BL_SPI2_RST); wait(10); gpio_set(GPIOD, BL_SPI2_RST); wait(10); gpio_set(GPIOD, BL_SPI2_WP); /* No WriteProtect, Set Chip select to 1(no select) */ gpio_set(GPIOB, BL_SPI2_NSS); /* Reset and disable SPI */ spi_reset(SPI2); /* Disable I2S */ SPI2_I2SCFGR = 0; /* CR1 */ spi_set_clock_phase_0(SPI2); /* CPHA = 0 */ spi_set_clock_polarity_0(SPI2); /* CPOL = 0 */ spi_send_msb_first(SPI2); /* LSB = 0 */ spi_set_full_duplex_mode(SPI2); /* RXONLY = 0 */ spi_set_unidirectional_mode(SPI2); /* BIDI = 0 */ spi_enable_software_slave_management(SPI2); /* SSM = 1 */ spi_set_nss_high(SPI2); /* SSI = 1 */ spi_set_master_mode(SPI2); /* MSTR = 1 */ spi_set_dff_8bit(SPI2); /* DFf = 8 bit */ // spi_enable_crc(SPI2); /* XXX: Too fast? Maybe DIV_4 will be better? */ spi_set_baudrate_prescaler(SPI2, SPI_CR1_BR_FPCLK_DIV_2); /* CR2 */ spi_enable_ss_output(SPI2); /* SSOE = 1 */ /* Disable regular interrupt flags */ spi_disable_tx_buffer_empty_interrupt(SPI2); spi_disable_rx_buffer_not_empty_interrupt(SPI2); spi_disable_error_interrupt(SPI2); /* Enabling RX/TX DMA flags */ spi_enable_tx_dma(SPI2); spi_enable_rx_dma(SPI2); d_print("REG: %lu:%lu\r\n", SPI_CR1(SPI2), SPI_CR2(SPI2)); spi_enable(SPI2); }
void baro_init() { gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); deselect_slave(); spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); spi_enable(SPI2); dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR); dma_set_read_from_memory(DMA1, DMA_CHANNEL3); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3); dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH); dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR); dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4); dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4); timer_reset(TIM4); timer_enable_irq(TIM4, TIM_DIER_UIE); timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 3200 / 16 = 200 Hz */ timer_set_prescaler(TIM4, 32); timer_set_period(TIM4, 5625); nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2); nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2); nvic_enable_irq(NVIC_TIM4_IRQ); nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ); read_calibration_data(); }
void setup(void) { // setup clock struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ]; rcc_clock_setup_hse_3v3(&clock); // enable GPIO clock - A (oled), B(oled), C (buttons) rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); // enable SPI clock rcc_periph_clock_enable(RCC_SPI1); // enable OTG FS clock rcc_periph_clock_enable(RCC_OTGFS); // enable RNG rcc_periph_clock_enable(RCC_RNG); RNG_CR |= RNG_CR_IE | RNG_CR_RNGEN; // set GPIO for buttons gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5); // set GPIO for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4); gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1); // enable SPI 1 for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7); gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7); // spi_disable_crc(SPI1); spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); // spi_enable_software_slave_management(SPI1); // spi_set_nss_high(SPI1); // spi_clear_mode_fault(SPI1); spi_enable(SPI1); // enable OTG_FS gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12); gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12); }
void spi_setup(void) { // SPI1 SCK gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_SCK); // SPI1 MOSI gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_MOSI); // SPI ChipSelect gpio_set_mode(MRF_SELECT_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, MRF_SELECT_PIN); gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_MISO); /* Setup SPI parameters. */ spi_init_master(MRF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); /* Ignore the stupid NSS pin. */ spi_enable_software_slave_management(MRF_SPI); spi_enable_ss_output(MRF_SPI); spi_set_nss_high(MRF_SPI); /* Finally enable the SPI. */ spi_enable(MRF_SPI); }
void spi_setup(void) { /* Configure GPIOs: SS=PB12, SCK=PB13, MISO=PB14 and MOSI=PA15 */ gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO12 | GPIO13 | GPIO15 ); //SPI input gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO14); //BUSSY C7 gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO7); gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO5 | GPIO6 ); /* Reset SPI, SPI_CR1 register cleared, SPI is disabled */ spi_reset(SPI2); /* Set up SPI in Master mode with: * Clock baud rate: 1/16 of peripheral clock frequency * Clock polarity: Idle Low * Clock phase: Data valid on 1nd clock pulse * Data frame format: 8-bit * Frame format: MSB First */ spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_LSBFIRST); spi_set_master_mode(SPI2); spi_enable_software_slave_management(SPI2); spi_enable_ss_output(SPI2); spi_set_nss_high(SPI2); spi_disable_error_interrupt(SPI2); spi_disable_crc(SPI2); /* Enable SPI2 periph. */ spi_enable(SPI2); }
static void spi_setup(void) { /* The DOGM128 display is connected to SPI2, so initialise it. */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN); spi_set_unidirectional_mode(DOGM128_SPI); /* We want to send only. */ spi_disable_crc(DOGM128_SPI); /* No CRC for this slave. */ spi_set_dff_8bit(DOGM128_SPI); /* 8-bit dataword-length */ spi_set_full_duplex_mode(DOGM128_SPI); /* Not receive-only */ /* We want to handle the CS signal in software. */ spi_enable_software_slave_management(DOGM128_SPI); spi_set_nss_high(DOGM128_SPI); /* PCLOCK/256 as clock. */ spi_set_baudrate_prescaler(DOGM128_SPI, SPI_CR1_BR_FPCLK_DIV_256); /* We want to control everything and generate the clock -> master. */ spi_set_master_mode(DOGM128_SPI); spi_set_clock_polarity_1(DOGM128_SPI); /* SCK idle state high. */ /* Bit is taken on the second (rising edge) of SCK. */ spi_set_clock_phase_1(DOGM128_SPI); spi_enable_ss_output(DOGM128_SPI); spi_enable(DOGM128_SPI); }
void setup(void) { // set SCB_CCR STKALIGN bit to make sure 8-byte stack alignment on exception entry is in effect. // This is not strictly necessary for the current TREZOR system. // This is here to comply with guidance from section 3.3.3 "Binary compatibility with other Cortex processors" // of the ARM Cortex-M3 Processor Technical Reference Manual. // According to section 4.4.2 and 4.4.7 of the "STM32F10xxx/20xxx/21xxx/L1xxxx Cortex-M3 programming manual", // STM32F2 series MCUs are r2p0 and always have this bit set on reset already. SCB_CCR |= SCB_CCR_STKALIGN; // setup clock struct rcc_clock_scale clock = rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_120MHZ]; rcc_clock_setup_hse_3v3(&clock); // enable GPIO clock - A (oled), B(oled), C (buttons) rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); // enable SPI clock rcc_periph_clock_enable(RCC_SPI1); // enable RNG rcc_periph_clock_enable(RCC_RNG); RNG_CR |= RNG_CR_RNGEN; // to be extra careful and heed the STM32F205xx Reference manual, Section 20.3.1 // we don't use the first random number generated after setting the RNGEN bit in setup random32(); // enable CSS (Clock Security System) RCC_CR |= RCC_CR_CSSON; // set GPIO for buttons gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_PULLUP, GPIO2 | GPIO5); // set GPIO for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO4); gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0 | GPIO1); // enable SPI 1 for OLED display gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO7); gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO7); // spi_disable_crc(SPI1); spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI1); // spi_enable_software_slave_management(SPI1); // spi_set_nss_high(SPI1); // spi_clear_mode_fault(SPI1); spi_enable(SPI1); // enable OTG_FS gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO10); gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12); gpio_set_af(GPIOA, GPIO_AF10, GPIO10 | GPIO11 | GPIO12); // enable OTG FS clock rcc_periph_clock_enable(RCC_OTGFS); // clear USB OTG_FS peripheral dedicated RAM memset_reg((void *) 0x50020000, (void *) 0x50020500, 0); }
bool Spi_stm32::init(void) { bool ret = true; // SPI IOs configurations // MISO init gpio_mode_setup(config_.miso_gpio_config.port, GPIO_MODE_AF, config_.miso_gpio_config.pull, config_.miso_gpio_config.pin ); gpio_set_af(config_.miso_gpio_config.port, config_.miso_gpio_config.alt_fct, config_.miso_gpio_config.pin ); // MOSI init gpio_mode_setup(config_.mosi_gpio_config.port, GPIO_MODE_AF, config_.mosi_gpio_config.pull, config_.mosi_gpio_config.pin ); gpio_set_af(config_.mosi_gpio_config.port, config_.mosi_gpio_config.alt_fct, config_.mosi_gpio_config.pin ); gpio_set_output_options(config_.mosi_gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, config_.mosi_gpio_config.pin ); // SCK init gpio_mode_setup(config_.sck_gpio_config.port, GPIO_MODE_AF, config_.sck_gpio_config.pull, config_.sck_gpio_config.pin ); gpio_set_af(config_.sck_gpio_config.port, config_.sck_gpio_config.alt_fct, config_.sck_gpio_config.pin ); gpio_set_output_options(config_.sck_gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, config_.sck_gpio_config.pin ); // SPI configuration switch (config_.spi_device) { case STM32_SPI1: rcc_periph_clock_enable(RCC_SPI1); break; case STM32_SPI2: rcc_periph_clock_enable(RCC_SPI2); break; case STM32_SPI3: rcc_periph_clock_enable(RCC_SPI3); break; default: ret = false; } if (config_.ss_mode_hard) { spi_disable_software_slave_management(spi_); spi_enable_ss_output(spi_); } // Warning: software slave managment not tested else { spi_enable_software_slave_management(spi_); } SPI_CR1(spi_) |= config_.clk_div; // Clock frequency spi_set_standard_mode(spi_, config_.mode); spi_enable(spi_); spi_set_master_mode(spi_); return ret; }