void NRF24L01_LOW_set_register(uint8_t regaddr, uint8_t val)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_W_REGISTER | regaddr);
spi_fast_shift(val);
NRF24L01_CSN_HIGH;
}
void nrf_send(uint8_t * value)
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
{
CE_LOW
TX_POWERUP // Power up NRF
nrf_config_register(STATUS,(1<<TX_DS)|(1<<MAX_RT)); // clear status register, write 1 to clear bit.
CSN_LOW // Pull down chip select
spi_fast_shift( FLUSH_TX ); // Write cmd to flush tx fifo
CSN_HIGH // Pull up chip select
CSN_LOW // Pull down chip select
spi_fast_shift( W_TX_PAYLOAD ); // Write cmd to write payload
spi_transmit_sync(value,PAYLOAD_WIDTH); // Write payload
CSN_HIGH // Pull up chip select
CE_HIGH // Start transmission
_delay_loop_1(4); // Short Delay to make sure CE is High for at least 10us
CE_LOW
// Wait until data is sent or MAX_RT flag
while(!(nrf_send_completed())); // This function return 1 if data was transmitted or after MAX_RT.
}
void NRF24L01_activate(void)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_ACTIVATE);
spi_fast_shift(0x73);
NRF24L01_CSN_HIGH;
}
/*******************************************************************************
* Clocks only one byte into the given MiRF register *
******************************************************************************/
void mirf_config_register(uint8_t reg, uint8_t value)
{
mirf_CSN_lo;
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_fast_shift(value);
mirf_CSN_hi;
}
/*******************************************************************************
* Sends a data package to the default address. Be sure to send the correct *
* amount of bytes as configured as payload on the receiver *
******************************************************************************/
void mirf_send(uint8_t * value, uint8_t len)
{
while (PTX) {} // Wait until last paket is send
mirf_CE_lo;
PTX = 1; // Set to transmitter mode
TX_POWERUP; // Power up
mirf_CSN_lo; // Pull down chip select
spi_fast_shift( FLUSH_TX ); // Write cmd to flush tx fifo
mirf_CSN_hi; // Pull up chip select
mirf_CSN_lo; // Pull down chip select
spi_fast_shift( W_TX_PAYLOAD ); // Write cmd to write payload
spi_transmit_sync(value,len); // Write payload
mirf_CSN_hi; // Pull up chip select
mirf_CE_hi; // Start transmission
while(mirf_is_sending());
mirf_CE_lo; // Deactivate transreceiver
RX_POWERUP; // Power up in receiving mode
mirf_CE_hi; // Listening for pakets
PTX = 0; // Set to receiving mode
// Reset status register for further interaction
mirf_config_register(STATUS,(1<<TX_DS)|(1<<MAX_RT));
//mirf_CE_lo;
POWERDOWN;
}
// Checks if MAX_RT has been reached
uint8_t mirf_max_rt_reached(void) {
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(R_REGISTER | (REGISTER_MASK & STATUS));
uint8_t status = spi_fast_shift(NOP); // Read status register
mirf_CSN_hi; // Pull up chip select
return status & (1<<MAX_RT);
}
// Checks if data is available for reading
uint8_t mirf_data_ready(void) {
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(R_REGISTER | (REGISTER_MASK & STATUS));
uint8_t status = spi_fast_shift(NOP); // Read status register
mirf_CSN_hi; // Pull up chip select
return status & (1<<RX_DR);
}
void mirf_config_register(uint8_t reg, uint8_t value)
// Clocks only one byte into the given MiRF register
{
mirf_CSN_lo;
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_fast_shift(value);
mirf_CSN_hi;
}
void nrf_config_register(uint8_t reg, uint8_t value)
// Clocks only one byte into the given NRF24L01+ register
{
CSN_LOW // ISP Slave on
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_fast_shift(value);
CSN_HIGH // ISP Slave off
}
// Flush RX and TX FIFO
void mirf_flush_rx_tx(void) {
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(FLUSH_RX); // Flush RX
mirf_CSN_hi; // Pull up chip select
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(FLUSH_TX); // Write cmd to flush tx fifo
mirf_CSN_hi; // Pull up chip select
}
///Initializes data transmission. Automatically sets the NRF24L01 to TX mode
extern void NRF24L01_send_data(uint8_t* data, uint8_t len)
{
NRF24L01_CE_LOW;
NRF24L01_set_tx();
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_FLUSH_TX);
NRF24L01_CSN_HIGH;
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_W_TX_PAYLOAD);
spi_transmit_sync(data, len);
NRF24L01_CSN_HIGH;
NRF24L01_CE_HIGH;
_delay_us(10);
NRF24L01_CE_LOW;
}
uint8_t NRF24L01_LOW_read_byte(uint8_t cmd)
{
NRF24L01_CSN_LOW;
uint8_t data = spi_fast_shift(cmd);
NRF24L01_CSN_HIGH;
return data;
}
void NRF24L01_write_ack_payload(uint8_t pipe, uint8_t* data, uint8_t len)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_W_ACK_PAYLOAD | pipe);
spi_transmit_sync(data, len);
NRF24L01_CSN_HIGH;
}
/*******************************************************************************
* Reads an array of bytes from the given start position in the MiRF registers *
******************************************************************************/
void mirf_read_register(uint8_t reg, uint8_t * value, uint8_t len)
{
mirf_CSN_lo;
spi_fast_shift(R_REGISTER | (REGISTER_MASK & reg));
spi_transfer_sync(value,value,len);
mirf_CSN_hi;
}
void NRF24L01_LOW_write_register(uint8_t regaddr, uint8_t* data, uint8_t len)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_W_REGISTER | regaddr);
spi_transmit_sync(data, len);
NRF24L01_CSN_HIGH;
}
/*******************************************************************************
* Writes an array of bytes into inte the MiRF registers. *
******************************************************************************/
void mirf_write_register(uint8_t reg, uint8_t * value, uint8_t len)
{
mirf_CSN_lo;
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_transmit_sync(value,len);
mirf_CSN_hi;
}
// Reads mirf_PAYLOAD bytes into data array
void mirf_get_data(uint8_t *data) {
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(R_RX_PAYLOAD); // Send cmd to read rx payload
spi_read_data(data, mirf_PAYLOAD); // Read payload
mirf_CSN_hi; // Pull up chip select
mirf_config_register(STATUS,(1<<RX_DR)); // Reset status register
}
void NRF24L01_LOW_read_register(uint8_t regaddr, uint8_t* data, uint8_t len)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_R_REGISTER | regaddr);
spi_transfer_sync(data, data, len);
NRF24L01_CSN_HIGH;
}
void mirf_read_register(uint8_t reg, uint8_t * value, uint8_t len)
// Reads an array of bytes from the given start position in the MiRF registers.
{
mirf_CSN_lo;
spi_fast_shift(R_REGISTER | (REGISTER_MASK & reg));
spi_transfer_sync(value,value,len);
mirf_CSN_hi;
}
void nrf_write_register(uint8_t reg, uint8_t * value, uint8_t len)
// Writes an array of bytes into into NRF24L01+ registers.
{
CSN_LOW
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_transmit_sync(value,len);
CSN_HIGH
}
void nrf_read_register(uint8_t reg, uint8_t * value, uint8_t len)
// Reads an array of bytes from the given start position in the NRF24L01+ registers.
{
CSN_LOW // ISP Slave on
spi_fast_shift(R_REGISTER | (REGISTER_MASK & reg));
spi_transfer_sync(value,value,len);
CSN_HIGH // ISP Slave off
}
void mirf_write_register(uint8_t reg, uint8_t * value, uint8_t len)
// Writes an array of bytes into inte the MiRF registers.
{
mirf_CSN_lo;
spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
spi_transmit_sync(value,len);
mirf_CSN_hi;
}
extern void NRF24L01_get_received_data(uint8_t* data, uint8_t len)
{
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_R_RX_PAYLOAD);
spi_transfer_sync(data, data, len);
NRF24L01_CSN_HIGH;
NRF24L01_LOW_set_register(NRF24L01_REG_STATUS, NRF24L01_MASK_STATUS_RX_DR);
}
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
void mirf_send(uint8_t *value, uint8_t len) {
PMODE = TXMODE; // Set to transmitter mode
TX_POWERUP; // Power up
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(FLUSH_TX); // Write cmd to flush tx fifo
mirf_CSN_hi; // Pull up chip select
mirf_CSN_lo; // Pull down chip select
spi_fast_shift(W_TX_PAYLOAD); // Write cmd to write payload
spi_transmit_sync(value, len); // Write payload
mirf_CSN_hi; // Pull up chip select
mirf_CE_hi; // Start transmission
_delay_us(15);
mirf_CE_lo;
}
uint8_t mirf_get_status(){
uint8_t rv;
mirf_CSN_lo;
rv = spi_fast_shift(W_REGISTER | (REGISTER_MASK & NOP));
mirf_CSN_hi;
return rv;
}
extern void mirf_get_data(uint8_t * data)
// Reads mirf_PAYLOAD bytes into data array
{
mirf_CSN_lo; // Pull down chip select
spi_fast_shift( R_RX_PAYLOAD ); // Send cmd to read rx payload
spi_transfer_sync(data,data,mirf_PAYLOAD); // Read payload
mirf_CSN_hi; // Pull up chip select
mirf_config_register(STATUS,(1<<RX_DR)); // Reset status register
}
/*******************************************************************************
* Checks if data is available for reading *
******************************************************************************/
extern uint8_t mirf_data_ready()
{
if (PTX) return 0;
uint8_t status;
// Read MiRF status
mirf_CSN_lo; // Pull down chip select
status = spi_fast_shift(NOP); // Read status register
mirf_CSN_hi; // Pull up chip select
return status & (1<<RX_DR);
}
extern void NRF24L01_send_data(uint8_t* data, uint8_t len)
{
NRF24L01_CE_LOW;
nrf24l01_config_t* config = malloc(sizeof(nrf24l01_config_t));
config->value = NRF24L01_LOW_get_register(NRF24L01_REG_CONFIG);
config->prim_rx = 0;
config->pwr_up = 1;
NRF24L01_LOW_set_register(NRF24L01_REG_CONFIG, config->value);
free(config);
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_FLUSH_TX);
NRF24L01_CSN_HIGH;
NRF24L01_CSN_LOW;
spi_fast_shift(NRF24L01_CMD_W_TX_PAYLOAD);
spi_transmit_sync(data, len);
NRF24L01_CSN_HIGH;
NRF24L01_CE_HIGH;
_delay_us(10);
NRF24L01_CE_LOW;
}
uint8_t nrf_command(uint8_t reg)
// Send command to radio without argument; Used for FLUSH_TX, FLUSH_RX, NOP. Return status register.
{
uint8_t status_reg;
CSN_LOW // ISP Slave on
status_reg = spi_fast_shift(reg);
CSN_HIGH // ISP Slave off
return status_reg;
}
void mirf_send(uint8_t * value, uint8_t len)
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
{
while (PTX) {} // Wait until last paket is send
mirf_CE_lo;
PTX = 1; // Set to transmitter mode
TX_POWERUP; // Power up
mirf_CSN_lo; // Pull down chip select
spi_fast_shift( FLUSH_TX ); // Write cmd to flush tx fifo
mirf_CSN_hi; // Pull up chip select
mirf_CSN_lo; // Pull down chip select
spi_fast_shift( W_TX_PAYLOAD ); // Write cmd to write payload
spi_transmit_sync(value,len); // Write payload
mirf_CSN_hi; // Pull up chip select
mirf_CE_hi; // Start transmission
}
