/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
int TestingTimes = 10;
int Counter = 0;
int TestData = 0;
#if SPI_IS_AS_MASTER
spi_t spi_master;
SPI0_IS_AS_SLAVE = 0;
spi_init(&spi_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
DBG_SSI_INFO("--------------------------------------------------------\n");
for(Counter = 0, TestData=0xFF; Counter < TestingTimes; Counter++) {
spi_master_write(&spi_master, TestData);
DBG_SSI_INFO("Master write: %02X\n", TestData);
TestData--;
}
spi_free(&spi_master);
#else
spi_t spi_slave;
SPI0_IS_AS_SLAVE = 1;
spi_init(&spi_slave, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
DBG_SSI_INFO("--------------------------------------------------------\n");
for(Counter = 0, TestData=0xFF; Counter < TestingTimes; Counter++) {
DBG_SSI_INFO(ANSI_COLOR_CYAN"Slave read : %02X\n"ANSI_COLOR_RESET,
spi_slave_read(&spi_slave));
TestData--;
}
spi_free(&spi_slave);
#endif
DBG_SSI_INFO("SPI Demo finished.\n");
for(;;);
}
void
sys_reset_bonds(struct sys *sys, struct sel *sel)
{
struct spi *spi;
struct pair pair;
int i, j, k, n, *map;
spi = spi_create();
n = sel_get_count(sel);
map = calloc(n, sizeof(int));
sel_iter_start(sel);
for (k = 0; sel_iter_next(sel, &i); k++) {
spi_add_point(spi, sys_get_atom_xyz(sys, i));
map[k] = i;
}
spi_compute(spi, 1.6);
n = spi_get_pair_count(spi);
for (k = 0; k < n; k++) {
pair = spi_get_pair(spi, k);
i = map[pair.i];
j = map[pair.j];
if (is_hydrogen(sys_get_atom_name(sys, i)) &&
is_hydrogen(sys_get_atom_name(sys, j)))
continue;
if (graph_edge_find(sys->graph, i, j) == NULL)
graph_edge_create(sys->graph, i, j, 1);
}
spi_free(spi);
free(map);
}
/*****************************************************************************
*
* SkPflUpdateConfig - Updates part of the config area in the parallel flash
*
* Description:
* This function updates part of configuration area in the parallel flash.
*
* Returns:
* 0 Success
* 1 Timeout
*/
static int SkPflUpdateConfig(
SK_AC *pAC,
SK_IOC IoC,
SK_U8 *pData, /* data buffer */
SK_U32 Offs, /* start offset in parallel flash (config area) for operation */
SK_U32 Len) /* length of changing data */
{
SK_U8 *pSpiBuf;
SK_U32 SectorSize;
SK_U32 StartSector;
SK_U32 EndSector;
int i;
// RARAsafe
return (1);
// RARA or SK_PFL_PART_MAIN?
SectorSize = pAC->pfl.pPflDev->SectorSize[SK_PFL_PART_INFO];
/* Determine the affected sectors. */
StartSector = Offs / SectorSize;
EndSector = (Offs + Len - 1) / SectorSize;
/* Allocate the necessary memory to temporary save the affected sectors. */
pSpiBuf = spi_malloc(((EndSector - StartSector) + 1) * SectorSize);
if (pSpiBuf == NULL) {
return (51);
}
/* Read out the affected sectors. */
if (SkPflManage(pAC, IoC, pSpiBuf, StartSector * SectorSize,
((EndSector - StartSector) + 1) * SectorSize, SPI_READ)) {
spi_free(pSpiBuf);
return (1);
}
/* Update the just read out data. */
for (i = 0; i < Len; i++) {
pSpiBuf[Offs + i - SPI_LSECT_OFF] = pData[i];
}
/* Erase the affected sectors. */
if (SkPflErase(pAC, IoC, StartSector * SectorSize,
((EndSector - StartSector) + 1) * SectorSize)) {
spi_free(pSpiBuf);
return (7);
}
/* Write the updated data back to the flash. */
if (SkPflManage(pAC, IoC, pSpiBuf, StartSector * SectorSize,
((EndSector - StartSector) + 1) * SectorSize, SPI_WRITE)) {
spi_free(pSpiBuf);
return (8);
}
spi_free(pSpiBuf);
return (0);
}
int main(void)
{
int ch;
bool_t eol=FALSE, spi_ini=FALSE, gpio_ini=FALSE;
spi_hndl_t spi_h;
gpio_hndl_t gpio_h;
if (gpio_init(&gpio_h, gpio_drv_io)!=LREC_SUCCESS) goto finish;
else gpio_ini=TRUE;
gpio_direction_output(&gpio_h, GPIO_CE, 0);
if (spi_init(&spi_h, 0, SPI_CS, SPI_MODE_0, FALSE, 8,
SPI_USE_DEF, SPI_USE_DEF, SPI_USE_DEF)!=LREC_SUCCESS) goto finish;
else spi_ini=TRUE;
signal(SIGINT, term_handler);
signal(SIGTERM, term_handler);
errno = 0;
hal_nrf_set_spi_hndl(&spi_h);
hal_nrf_set_power_mode(HAL_NRF_PWR_UP);
usleep(1500);
NRF_EXEC(hal_nrf_set_operation_mode(HAL_NRF_PRX));
for (ch=0; ch<128 && !scan_finish; ch++)
{
int i;
if (eol) printf("\n");
NRF_EXEC(hal_nrf_set_rf_channel(ch));
assert(hal_nrf_get_rf_channel()==ch);
chip_enable();
for (i=0; i<500; i++) {
if (hal_nrf_get_carrier_detect()) break;
usleep(1000);
}
if (i<500) {
if (!eol) printf("\n");
printf("Carrier detected on channel %d", ch);
eol=TRUE;
} else {
printf(".");
fflush(stdout);
eol = (!((ch+1)%10) ? TRUE : FALSE);
}
chip_disable();
}
if (!eol) printf("\n");
finish:
if (errno==ECOMM) printf("SPI communication error\n");
if (spi_ini) spi_free(&spi_h);
if (gpio_ini) gpio_free(&gpio_h);
return 0;
}
/**
* @brief Main program.
* @param None
* @retval None
*/
void main(void)
{
int Counter = 0;
int i;
#if SPI_IS_AS_MASTER
spi_init(&spi_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_frequency(&spi_master, SCLK_FREQ);
spi_format(&spi_master, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 0);
// wait Slave ready
wait_ms(1000);
while (Counter < TEST_LOOP) {
DBG_8195A("======= Test Loop %d =======\r\n", Counter);
for (i=0;i<TEST_BUF_SIZE;i++) {
TestBuf[i] = i;
}
spi_irq_hook(&spi_master, master_tr_done_callback, (uint32_t)&spi_master);
DBG_8195A("SPI Master Write Test==>\r\n");
TrDone = 0;
#if SPI_DMA_DEMO
spi_master_write_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
#else
spi_master_write_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Master Wait Write Done...\r\n");
while(TrDone == 0) {
wait_ms(10);
i++;
}
DBG_8195A("SPI Master Write Done!!\r\n");
DBG_8195A("SPI Master Read Test==>\r\n");
DBG_8195A("Wait 5 sec for SPI Slave get ready...\r\n");
for (i=0;i<5;i++) {
wait_ms(1000);
}
_memset(TestBuf, 0, TEST_BUF_SIZE);
spi_flush_rx_fifo(&spi_master);
TrDone = 0;
#if SPI_DMA_DEMO
spi_master_read_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
#else
spi_master_read_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Master Wait Read Done...\r\n");
while(TrDone == 0) {
wait_ms(10);
i++;
}
DBG_8195A("SPI Master Read Done!!\r\n");
__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Master Read Data:");
Counter++;
}
spi_free(&spi_master);
DBG_8195A("SPI Master Test <==\r\n");
#else
spi_init(&spi_slave, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
spi_format(&spi_slave, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 1);
while (spi_busy(&spi_slave)) {
DBG_8195A("Wait SPI Bus Ready...\r\n");
wait_ms(1000);
}
while (Counter < TEST_LOOP) {
DBG_8195A("======= Test Loop %d =======\r\n", Counter);
_memset(TestBuf, 0, TEST_BUF_SIZE);
DBG_8195A("SPI Slave Read Test ==>\r\n");
spi_irq_hook(&spi_slave, slave_tr_done_callback, (uint32_t)&spi_slave);
TrDone = 0;
spi_flush_rx_fifo(&spi_slave);
#if SPI_DMA_DEMO
spi_slave_read_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
#else
spi_slave_read_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Slave Wait Read Done...\r\n");
while(TrDone == 0) {
wait_ms(100);
i++;
if (i>150) {
DBG_8195A("SPI Slave Wait Timeout\r\n");
break;
}
}
__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Slave Read Data:");
// Slave Write Test
DBG_8195A("SPI Slave Write Test ==>\r\n");
TrDone = 0;
#if SPI_DMA_DEMO
spi_slave_write_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
#else
spi_slave_write_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
#endif
i=0;
DBG_8195A("SPI Slave Wait Write Done...\r\n");
while(TrDone == 0) {
wait_ms(100);
i++;
if (i> 200) {
DBG_8195A("SPI Slave Write Timeout...\r\n");
break;
}
}
DBG_8195A("SPI Slave Write Done!!\r\n");
Counter++;
}
spi_free(&spi_slave);
#endif
DBG_8195A("SPI Demo finished.\n");
for(;;);
}
