/**
* @function: spi_read_word
* @brief: Reads a word from the SPI interface
*/
uint16_t
spi_read_word(void)
{
uint16_t result = 0;
result = spi_read_byte() << 8;
result |= spi_read_byte();
return result;
}
uint8_t sd_read_multi_sector(uint32_t addr, uint8_t sector_num, uint8_t * buffer) {
uint16_t i, time = 0;
uint8_t r1;
//set CS low
cs_enable();
//send CMD18 for multiple blocks read
r1 = sd_send_cmd(CMD18, addr << 9, 0xff);
//if CMD18 fail,return
if (r1 != 0x00) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
//read sector_num sector
do {
//continually read till get start byte
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 30000 || ((r1 & 0xf0) == 0x00 && (r1 & 0x0f))) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0xfe);
time = 0;
//read 512 Bits of data
for (i = 0; i < 512; i++) {
*buffer++ = spi_read_byte();
}
//read two bits of CRC
spi_read_byte();
spi_read_byte();
} while (--sector_num);
time = 0;
//stop multiple reading
r1 = sd_send_cmd(CMD12, 0, 0xff);
//set CS high and send 8 clocks
cs_disable();
return 0;
}
uint8_t get_csd_reg(csd_t* csd) {
uint8_t r1;
uint16_t i, time = 0;
uint8_t * buffer = (uint8_t*) csd;
//set CS low
cs_enable();
//send CMD10 for CID read or CMD9 for CSD
do {
r1 = sd_send_cmd(CMD9, 0, 0xff);
time++;
//if time out,set CS high and return r1
if (time > 254) {
//set CS high and send 8 clocks
cs_disable();
return -1;
}
} while (r1 != 0x00);
time = 0;
//continually read till get 0xfe
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 30000) {
//set CS high and send 8 clocks
cs_disable();
return -1;
}
} while (r1 != 0xfe);
//read 512 Bits of data
for (i = 0; i < 16; i++) {
*buffer++ = spi_read_byte();
}
//read two bits of CRC
spi_read_byte();
spi_read_byte();
//set CS high and send 8 clocks
cs_disable();
return 0;
}
uint8_t sd_read_sector(uint32_t addr, uint8_t * buffer) {
uint8_t r1;
uint16_t i, time = 0;
if(sd_type != SD_CARD_TYPE_SDHC) addr <<= 9;
// serial_printf("read addr=%x\n",addr);
//set CS low
cs_enable();
//send CMD17 for single block read
r1 = sd_send_cmd(CMD17, addr, 0x55);
//if CMD17 fail,return
if (r1 != 0x00) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
//continually read till get the start byte 0xfe
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 30000) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0xfe);
//read 512 Bits of data
for (i = 0; i < 512; i++) {
buffer[i] = spi_read_byte();
}
//read two bits of CRC
spi_read_byte();
spi_read_byte();
//set CS high and send 8 clocks
cs_disable();
return 0;
}
/*
* Function to read bytes number of data from the Input FIFO
*/
static int __blsp_spi_read(struct ipq_spi_slave *ds, u8 *data_buffer,
unsigned int bytes)
{
uint32_t val;
unsigned int i;
unsigned int fifo_count;
int ret = SUCCESS;
int state_config;
/* Configure no of bytes to read */
state_config = config_spi_state(ds, QUP_STATE_RESET);
if (state_config)
return state_config;
/* Configure input and output enable */
enable_io_config(ds, 0, bytes);
write32(ds->regs->qup_mx_input_count, bytes);
state_config = config_spi_state(ds, QUP_STATE_RUN);
if (state_config)
return state_config;
while (bytes) {
ret = check_fifo_status(ds->regs->qup_operational);
if (ret != SUCCESS)
goto out;
val = read32(ds->regs->qup_operational);
if (val & INPUT_SERVICE_FLAG) {
/*
* acknowledge to hw that software will
* read input data
*/
val &= INPUT_SERVICE_FLAG;
write32(ds->regs->qup_operational, val);
fifo_count = ((bytes > SPI_INPUT_BLOCK_SIZE) ?
SPI_INPUT_BLOCK_SIZE : bytes);
for (i = 0; i < fifo_count; i++) {
*data_buffer = spi_read_byte(ds);
data_buffer++;
bytes--;
}
}
}
out:
/*
* Put the SPI Core back in the Reset State
* to end the transfer
*/
(void)config_spi_state(ds, QUP_STATE_RESET);
return ret;
}
void spi_read(uint8_t addr , uint8_t *data, uint8_t len)
{
uint8_t i;
spi_start();
spi_write_byte(addr);
for (i = 0; i < len; i++){
*((data + i)) = spi_read_byte();
}
spi_stop();
}
void spi_read(unsigned char* buf, int len)
{
int i;
// spi_init();
// ss_enable(1);
// delay_us(10);
// for (i=0; i<len; i++)
// buf[i] = spi_read_byte();
// delay_us(10);
// ss_enable(0);
for (i=0; i<len; i++)
buf[i] = spi_read_byte();
}
uint8_t sd_send_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) {
uint8_t r1, time = 0;
//send the command,arguments and CRC
spi_write_byte((cmd & 0x3f) | 0x40);
spi_write_byte(arg >> 24);
spi_write_byte(arg >> 16);
spi_write_byte(arg >> 8);
spi_write_byte(arg);
spi_write_byte(crc);
//read the respond until responds is not '0xff' or timeout
do {
r1 = spi_read_byte();
time++;
//if time out,return
if (time > 254) break;
} while (r1 == 0xff);
return r1;
}
static unsigned int spi_read(ice1712_t *ice, unsigned int dev, unsigned int reg)
{
unsigned int val;
snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev & ~1); /* WRITE */
spi_send_byte(ice, reg); /* MAP */
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
set_gpio_bit(ice, PONTIS_CS_CS, 0);
spi_send_byte(ice, dev | 1); /* READ */
val = spi_read_byte(ice);
/* trigger */
set_gpio_bit(ice, PONTIS_CS_CS, 1);
udelay(1);
/* restore */
snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
return val;
}
uint8_t sd_init() {
uint8_t i,r1, time = 0;
//sd reset
sd_reset();
//set CS low
cs_enable();
//check interface operating condition
r1 = sd_send_cmd(CMD8, 0x000001aa, 0x87);
//if support Ver1.x,but do not support Ver2.0,set CS high and return r1
if (r1 == 0x05) {
//set CS high and send 8 clocks
cs_disable();
sd_type = SD_CARD_TYPE_SD1;
return r1;
}
//read the other 4 bytes of response(the response of CMD8 is 5 bytes)
for(i=0;i<4;i++) r1 = spi_read_byte();
sd_type = SD_CARD_TYPE_SD2;
serial_printf("support Ver2.0\n");
//send CMD55+ACMD41 to initial SD card
do {
do {
r1 = sd_send_cmd(CMD55, 0, 0xff);
time++;
//if time out,set CS high and return r1
if (time > 254){
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0x01);
r1 = sd_send_cmd(ACMD41, 0x40000000, 0xff);
//send CMD1 to initial SD card
// r1 = sd_send_cmd(CMD1,0x00ffc000,0xff);
time++;
//if time out,set CS high and return r1
if (time > 254) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0x00);
// if SD2 read OCR register to check for SDHC card
r1 = sd_send_cmd(CMD58,0,0xFF);
if (r1 == 0x05) {
cs_disable();
return r1;
}
r1 = spi_read_byte();
if(r1 & 0x40){
sd_type = SD_CARD_TYPE_SDHC;
serial_printf("SDHC card \n");
}
for(i=0;i<3;i++) r1 = spi_read_byte();
//set CS high and send 8 clocks
cs_disable();
serial_printf("sd_init ok\n");
return 0;
}
uint8_t sd_write_multi_sector(uint32_t addr, uint8_t sector_num, uint8_t * buffer) {
uint16_t i, time = 0;
uint8_t r1;
//set CS low
cs_enable();
//send CMD25 for multiple block read
r1 = sd_send_cmd(CMD25, addr << 9, 0xff);
//if CMD25 fail,return
if (r1 != 0x00) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
do {
do {
//send several dummy clocks
for (i = 0; i < 5; i++) {
spi_write_byte(0xff);
}
//write start byte
spi_write_byte(0xfc);
//write 512 byte of data
for (i = 0; i < 512; i++) {
spi_write_byte(*buffer++);
}
//write 2 byte of CRC
spi_write_byte(0xff);
spi_write_byte(0xff);
//read response
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 254) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while ((r1 & 0x1f) != 0x05);
time = 0;
//check busy
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 30000) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0xff);
time = 0;
} while (--sector_num);
//send stop byte
spi_write_byte(0xfd);
//check busy
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 30000) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0xff);
//set CS high and send 8 clocks
cs_disable();
return 0;
}
uint8_t sd_write_sector(uint32_t addr, uint8_t * buffer) {
uint16_t i, time = 0;
uint8_t r1;
//set CS low
cs_enable();
do {
do {
//send CMD24 for single block write
r1 = sd_send_cmd(CMD24, addr << 9, 0xff);
time++;
//if time out,set CS high and return r1
if (time > 254) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0x00);
time = 0;
//send some dummy clocks
for (i = 0; i < 5; i++) {
spi_write_byte(0xff);
}
//write start byte
spi_write_byte(0xfe);
//write 512 bytes of data
for (i = 0; i < 512; i++) {
spi_write_byte(buffer[i]);
}
//write 2 bytes of CRC
spi_write_byte(0xff);
spi_write_byte(0xff);
//read response
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 254) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while ((r1 & 0x1f) != 0x05);
time = 0;
//check busy
do {
r1 = spi_read_byte();
time++;
//if time out,set CS high and return r1
if (time > 60000) {
//set CS high and send 8 clocks
cs_disable();
return r1;
}
} while (r1 != 0xff);
//set CS high and send 8 clocks
cs_disable();
return 0;
}
/*
* Function to write data to the Output FIFO
*/
static int __blsp_spi_write(struct ipq_spi_slave *ds, const u8 *cmd_buffer,
unsigned int bytes)
{
uint32_t val;
unsigned int i;
unsigned int write_len = bytes;
unsigned int read_len = bytes;
unsigned int fifo_count;
int ret = SUCCESS;
int state_config;
state_config = config_spi_state(ds, QUP_STATE_RESET);
if (state_config)
return state_config;
/* No of bytes to be written in Output FIFO */
write32(ds->regs->qup_mx_output_count, bytes);
write32(ds->regs->qup_mx_input_count, bytes);
state_config = config_spi_state(ds, QUP_STATE_RUN);
if (state_config)
return state_config;
/* Configure input and output enable */
enable_io_config(ds, write_len, read_len);
/*
* read_len considered to ensure that we read the dummy data for the
* write we performed. This is needed to ensure with WR-RD transaction
* to get the actual data on the subsequent read cycle that happens
*/
while (write_len || read_len) {
ret = check_fifo_status(ds->regs->qup_operational);
if (ret != SUCCESS)
goto out;
val = read32(ds->regs->qup_operational);
if (val & OUTPUT_SERVICE_FLAG) {
/*
* acknowledge to hw that software will write
* expected output data
*/
val &= OUTPUT_SERVICE_FLAG;
write32(ds->regs->qup_operational, val);
if (write_len > SPI_OUTPUT_BLOCK_SIZE)
fifo_count = SPI_OUTPUT_BLOCK_SIZE;
else
fifo_count = write_len;
for (i = 0; i < fifo_count; i++) {
/* Write actual data to output FIFO */
spi_write_byte(ds, *cmd_buffer);
cmd_buffer++;
write_len--;
}
}
if (val & INPUT_SERVICE_FLAG) {
/*
* acknowledge to hw that software
* will read input data
*/
val &= INPUT_SERVICE_FLAG;
write32(ds->regs->qup_operational, val);
if (read_len > SPI_INPUT_BLOCK_SIZE)
fifo_count = SPI_INPUT_BLOCK_SIZE;
else
fifo_count = read_len;
for (i = 0; i < fifo_count; i++) {
/* Read dummy data for the data written */
(void)spi_read_byte(ds);
/* Decrement the read count after reading the
* dummy data from the device. This is to make
* sure we read dummy data before we write the
* data to fifo
*/
read_len--;
}
}
}
out:
/*
* Put the SPI Core back in the Reset State
* to end the transfer
*/
(void)config_spi_state(ds, QUP_STATE_RESET);
return ret;
}