/**
* @brief Read sequential registers from the LIS3DH.
*
* @param[in] dev Device descriptor
* @param[in] reg The source register starting address
* @param[in] len Number of bytes to read
* @param[out] buf The values of the source registers will be written here
*
* @return 0 on success
* @return -1 on error
*/
static int lis3dh_read_regs(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t len,
uint8_t *buf)
{
/* Set READ MULTIPLE mode */
uint8_t addr = (reg & LIS3DH_SPI_ADDRESS_MASK) | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_regs(dev->spi, addr, NULL, (char *)buf, len) < 0) {
/* Transfer error */
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return 0;
}
FPGA_STATUS fpga_spi_loopback(uint8_t* data,uint32_t data_len)
{
FPGA_STATUS ret;
uint8_t i,rcvd[100];
uint8_t writecmd = CMDPKT_FPGA_WRITE,readcmd=CMDPKT_FPGA_READ;
//initialise SPI
ret = fpga_spiclaim(SPI_FPGA_OPFREQ);
if (ret) {
spi_release();
return FAIL;
}
//transmit data
spi_xfer(1,&writecmd,NULL,0);
spi_xfer(data_len,data,NULL,0);
spi_release();
delay (100);
platform_write("DATA sent successfully \n");
//receive the data
ret = fpga_spiclaim(SPI_FPGA_OPFREQ);
if (ret) {
spi_release();
return FAIL;
}
spi_cmd_read(&readcmd,1,rcvd,data_len);
//verify the data
for(i=0;i<data_len;i++)
{
if(rcvd[i]=!data[i])
platform_write("error occurred for byte %d expected :%d received %d",i,data[i],rcvd[i]);
else
platform_write("DATA verification successful \n");
}
spi_release();
return SUCCESS;
}
int lis3dh_read_xyz(const lis3dh_t *dev, lis3dh_data_t *acc_data)
{
uint8_t i;
/* Set READ MULTIPLE mode */
static const uint8_t addr = (LIS3DH_REG_OUT_X_L | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK);
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_regs(dev->spi, addr, NULL, (char *)acc_data,
sizeof(lis3dh_data_t)) != sizeof(lis3dh_data_t)) {
/* Transfer error */
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
/* Scale to milli-G */
for (i = 0; i < 3; ++i) {
int32_t tmp = (int32_t)(((int16_t *)acc_data)[i]);
tmp *= dev->scale;
tmp /= 32768;
(((int16_t *)acc_data)[i]) = (int16_t)tmp;
}
return 0;
}
int cmd_init_master(int argc, char **argv)
{
int res;
spi_master = -1;
if (parse_spi_dev(argc, argv) < 0) {
return 1;
}
spi_acquire(spi_dev);
res = spi_init_master(spi_dev, spi_mode, spi_speed);
spi_release(spi_dev);
if (res < 0) {
printf("spi_init_master: error initializing SPI_%i device (code %i)\n",
spi_dev, res);
return 1;
}
res = gpio_init(spi_cs, GPIO_OUT);
if (res < 0){
printf("gpio_init: error initializing GPIO_%ld as CS line (code %i)\n",
(long)spi_cs, res);
return 1;
}
gpio_set(spi_cs);
spi_master = 1;
printf("SPI_%i successfully initialized as master, cs: GPIO_%ld, mode: %i, speed: %i\n",
spi_dev, (long)spi_cs, spi_mode, spi_speed);
return 0;
}
int kw2xrf_spi_init(spi_t spi, spi_speed_t spi_speed,
gpio_t cs_pin)
{
int res;
kw2xrf_cs_pin = cs_pin; /**< for later reference */
kw2xrf_spi = spi;
#if KW2XRF_SHARED_SPI
spi_acquire(kw2xrf_spi);
#endif
res = spi_init_master(kw2xrf_spi, SPI_CONF_FIRST_RISING, spi_speed);
#if KW2XRF_SHARED_SPI
spi_release(kw2xrf_spi);
gpio_init_out(kw2xrf_cs_pin, GPIO_NOPULL);
gpio_set(kw2xrf_cs_pin);
#endif
if (res < 0) {
DEBUG("kw2xrf_spi_init: error initializing SPI_%i device (code %i)\n",
kw2xrf_spi, res);
return -1;
}
return 0;
}
void kw2xrf_spi_transfer_tail(void)
{
#if KW2XRF_SHARED_SPI
gpio_set(kw2xrf_cs_pin);
spi_release(kw2xrf_spi);
#endif
}
int cmd_init_slave(int argc, char **argv)
{
int res;
spi_master = -1;
if (parse_spi_dev(argc, argv) < 0) {
return 1;
}
spi_acquire(spi_dev);
res = spi_init_slave(spi_dev, spi_mode, slave_on_data);
spi_release(spi_dev);
if (res < 0) {
printf("spi_init_slave: error initializing SPI_%i device (code: %i)\n",
spi_dev, res);
return 1;
}
res = gpio_init_int(spi_cs, GPIO_IN, GPIO_FALLING, slave_on_cs, 0);
if (res < 0){
printf("gpio_init_int: error initializing GPIO_%ld as CS line (code %i)\n",
(long)spi_cs, res);
return 1;
}
spi_master = 0;
printf("SPI_%i successfully initialized as slave, cs: GPIO_%ld, mode: %i\n",
spi_dev, (long)spi_cs, spi_mode);
return 0;
}
static void cmd(encx24j600_t *dev, char cmd) {
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_byte(dev->spi, cmd, NULL);
gpio_set(dev->cs);
spi_release(dev->spi);
}
static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_READ;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (src > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (src & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, (char)cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
uint8_t u8x8_byte_riotos_hw_spi(u8x8_t *u8g2, uint8_t msg, uint8_t arg_int, void *arg_ptr)
{
spi_t dev = (spi_t) u8g2->dev;
switch (msg) {
case U8X8_MSG_BYTE_SEND:
spi_transfer_bytes(dev, GPIO_UNDEF, true,
arg_ptr, NULL, (size_t)arg_int);
break;
case U8X8_MSG_BYTE_INIT:
spi_init_pins(dev);
break;
case U8X8_MSG_BYTE_SET_DC:
u8x8_gpio_SetDC(u8g2, arg_int);
break;
case U8X8_MSG_BYTE_START_TRANSFER:
spi_acquire(dev, GPIO_UNDEF,
u8x8_spi_mode_to_spi_conf(u8g2->display_info->spi_mode),
u8x8_pulse_width_to_spi_speed(u8g2->display_info->sck_pulse_width_ns));
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_enable_level);
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->post_chip_enable_wait_ns, NULL);
break;
case U8X8_MSG_BYTE_END_TRANSFER:
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->pre_chip_disable_wait_ns, NULL);
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_disable_level);
spi_release(dev);
break;
default:
return 0;
}
return 1;
}
static void cmdn(encx24j600_t *dev, uint8_t cmd, char *out, char *in, int len) {
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_byte(dev->spi, cmd, NULL);
spi_transfer_bytes(dev->spi, out, in, len);
gpio_set(dev->cs);
spi_release(dev->spi);
}
static inline void enc_spi_transfer(encx24j600_t *dev, char *out, char *in, int len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_bytes(dev->spi, out, in, len);
gpio_set(dev->cs);
spi_release(dev->spi);
}
uint16_t cc2420_reg_read(const cc2420_t *dev, const uint8_t addr)
{
network_uint16_t tmp;
spi_acquire(SPI_BUS, SPI_CS, SPI_MODE, SPI_CLK);
spi_transfer_regs(SPI_BUS, SPI_CS, (CC2420_REG_READ | addr),NULL, &tmp, 2);
spi_release(SPI_BUS);
return byteorder_ntohs(tmp);
}
/**
* @brief Write a register value to the sensor
*
* @param[in] dev device descriptor
* @param[in] addr register address
* @param[in] len register size
* @param[in] buf source buffer
*/
static void ds3234_write_reg(const ds3234_params_t *dev, uint8_t addr, size_t len, const uint8_t *buf)
{
uint8_t command = DS3234_CMD_WRITE | addr;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE_3, dev->clk);
/* Perform the transaction */
spi_transfer_regs(dev->spi, dev->cs, command, buf, NULL, len);
/* Release the bus for other threads. */
spi_release(dev->spi);
}
uint8_t cc2420_strobe(const cc2420_t *dev, const uint8_t command)
{
uint8_t res;
spi_acquire(SPI_BUS, SPI_CS, SPI_MODE, SPI_CLK);
res = spi_transfer_byte(SPI_BUS, SPI_CS, false, command);
spi_release(SPI_BUS);
return res;
}
void cc2420_reg_write(const cc2420_t *dev,
const uint8_t addr,
const uint16_t value)
{
uint16_t tmp = byteorder_htons(value).u16;
spi_acquire(SPI_BUS, SPI_CS, SPI_MODE, SPI_CLK);
spi_transfer_regs(SPI_BUS, SPI_CS, (CC2420_REG_WRITE | addr), &tmp, NULL, 2);
spi_release(SPI_BUS);
}
void cc110x_writeburst_reg(uint8_t addr, char *src, uint8_t count)
{
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_regs(CC110X_SPI, addr | CC1100_WRITE_BURST, src, 0, count);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
}
void cc110x_write_reg(uint8_t addr, uint8_t value)
{
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_reg(CC110X_SPI, addr, value, 0);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
}
static void _write(pcd8544_t *dev, uint8_t is_data, char data)
{
/* set command or data mode */
gpio_write(dev->mode, is_data);
/* write byte to LCD */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_byte(dev->spi, data, 0);
gpio_set(dev->cs);
spi_release(dev->spi);
}
int nrf24l01p_read_payload(const nrf24l01p_t *dev, char *answer, unsigned int size)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_regs(dev->spi, dev->cs, CMD_R_RX_PAYLOAD, NULL, answer, size);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Release the bus for other threads. */
spi_release(dev->spi);
return 0;
}
void cc110x_writeburst_reg(cc110x_t *dev, uint8_t addr, const char *src, uint8_t count)
{
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
spi_transfer_regs(dev->params.spi, addr | CC110X_WRITE_BURST, (char *)src, 0, count);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
}
void cc110x_write_reg(cc110x_t *dev, uint8_t addr, uint8_t value)
{
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
spi_transfer_reg(dev->params.spi, addr, value, 0);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
}
void flash_read_id(uint8_t idbuf[3])
{
uint8_t out = SPI_FLASH_READ_ID;
P5Q_LOCK();
spi_select_p5q();
spi_write(&out, 1);
spi_read(idbuf, 3);
spi_release();
P5Q_UNLOCK();
}
void at86rf2xx_reg_write(const at86rf2xx_t *dev,
const uint8_t addr,
const uint8_t value)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
AT86RF2XX_ACCESS_REG | AT86RF2XX_ACCESS_WRITE | addr,
value, 0);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
int nrf24l01p_write_reg(const nrf24l01p_t *dev, char reg, char write)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_reg(dev->spi, dev->cs,
(CMD_W_REGISTER | (REGISTER_MASK & reg)), (uint8_t)write);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
uint8_t cc110x_strobe(uint8_t c)
{
char result;
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_byte(CC110X_SPI, c, &result);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
return (uint8_t) result;
}
static void da14583_spi_flash_release(void)
{
// Power down flash
spi_flash_power_down();
// Release SPI controller
spi_release();
// Release internal flash GPIOs
GPIO_ConfigurePin( DA14583_SPI_FLASH_EN_GPIO_PORT, DA14583_SPI_FLASH_EN_GPIO_PIN, OUTPUT, PID_GPIO, true );
GPIO_ConfigurePin( DA14583_SPI_FLASH_CLK_GPIO_PORT, DA14583_SPI_FLASH_CLK_GPIO_PIN, INPUT_PULLDOWN, PID_GPIO, false );
GPIO_ConfigurePin( DA14583_SPI_FLASH_DO_GPIO_PORT, DA14583_SPI_FLASH_DO_GPIO_PIN, INPUT_PULLDOWN, PID_GPIO, false );
GPIO_ConfigurePin( DA14583_SPI_FLASH_DI_GPIO_PORT, DA14583_SPI_FLASH_DI_GPIO_PIN, INPUT_PULLDOWN, PID_GPIO, false );
}
int nrf24l01p_read_reg(const nrf24l01p_t *dev, char reg, char *answer)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
*answer = (char)spi_transfer_reg(dev->spi, dev->cs,
(CMD_R_REGISTER | (REGISTER_MASK & reg)),
CMD_NOP);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
int nrf24l01p_preload(const nrf24l01p_t *dev, char *data, unsigned int size)
{
size = (size <= 32) ? size : 32;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_regs(dev->spi, dev->cs, CMD_W_TX_PAYLOAD, data, NULL, size);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
void at86rf2xx_fb_read(const at86rf2xx_t *dev,
uint8_t *data,
const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_byte(dev->spi,
AT86RF2XX_ACCESS_FB | AT86RF2XX_ACCESS_READ,
NULL);
spi_transfer_bytes(dev->spi, NULL, (char *)data, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
