int ws2812_write(ws2812_t *dev, char *b, unsigned len) {
static char reset_pulse[20] = {0};
spi_acquire(dev->spi);
/* int i = 0; */
/* for (i=0; i<len; i++) */
/* printf("%x.", b[i]); */
/* printf("\n"); */
spi_transfer_bytes(dev->spi, b, NULL, len);
spi_transfer_bytes(dev->spi, reset_pulse, NULL, sizeof(reset_pulse));
spi_release(dev->spi);
return 0;
}
static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_READ;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (src > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (src & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, (char)cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
void cmd_transfer(int argc, char **argv)
{
int res;
char *hello = "Hello";
if (spi_master != 1) {
puts("error: node is not initialized as master, please do so first");
return;
}
if (argc < 2) {
puts("No data to transfer given, will transfer 'Hello' to device");
}
else {
hello = argv[1];
}
/* do the actual data transfer */
gpio_clear(spi_cs);
res = spi_transfer_bytes(spi_dev, hello, buffer, strlen(hello));
gpio_set(spi_cs);
/* look at the results */
if (res < 0) {
printf("error: unable to transfer data to slave (code: %i)\n", res);
}
else {
printf("Transfered %i bytes:\n", res);
print_bytes("MOSI", hello, res);
print_bytes("MISO", buffer, res);
}
}
static void _write(pcd8544_t *dev, uint8_t is_data, char data)
{
/* set command or data mode */
gpio_write(dev->mode, is_data);
/* write byte to LCD */
spi_transfer_bytes(dev->spi, dev->cs, false, (uint8_t *)&data, NULL, 1);
}
uint8_t u8x8_byte_riotos_hw_spi(u8x8_t *u8g2, uint8_t msg, uint8_t arg_int, void *arg_ptr)
{
spi_t dev = (spi_t) u8g2->dev;
switch (msg) {
case U8X8_MSG_BYTE_SEND:
spi_transfer_bytes(dev, GPIO_UNDEF, true,
arg_ptr, NULL, (size_t)arg_int);
break;
case U8X8_MSG_BYTE_INIT:
spi_init_pins(dev);
break;
case U8X8_MSG_BYTE_SET_DC:
u8x8_gpio_SetDC(u8g2, arg_int);
break;
case U8X8_MSG_BYTE_START_TRANSFER:
spi_acquire(dev, GPIO_UNDEF,
u8x8_spi_mode_to_spi_conf(u8g2->display_info->spi_mode),
u8x8_pulse_width_to_spi_speed(u8g2->display_info->sck_pulse_width_ns));
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_enable_level);
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->post_chip_enable_wait_ns, NULL);
break;
case U8X8_MSG_BYTE_END_TRANSFER:
u8g2->gpio_and_delay_cb(u8g2, U8X8_MSG_DELAY_NANO, u8g2->display_info->pre_chip_disable_wait_ns, NULL);
u8x8_gpio_SetCS(u8g2, u8g2->display_info->chip_disable_level);
spi_release(dev);
break;
default:
return 0;
}
return 1;
}
static void cmdn(encx24j600_t *dev, uint8_t cmd, char *out, char *in, int len) {
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_byte(dev->spi, cmd, NULL);
spi_transfer_bytes(dev->spi, out, in, len);
gpio_set(dev->cs);
spi_release(dev->spi);
}
static inline void enc_spi_transfer(encx24j600_t *dev, char *out, char *in, int len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs);
spi_transfer_bytes(dev->spi, out, in, len);
gpio_set(dev->cs);
spi_release(dev->spi);
}
void at86rf2xx_fb_read(const at86rf2xx_t *dev,
uint8_t *data,
const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_byte(dev->spi,
AT86RF2XX_ACCESS_FB | AT86RF2XX_ACCESS_READ,
NULL);
spi_transfer_bytes(dev->spi, NULL, (char *)data, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
void at86rf2xx_sram_write(const at86rf2xx_t *dev,
const uint8_t offset,
const uint8_t *data,
const size_t len)
{
spi_acquire(dev->spi);
gpio_clear(dev->cs_pin);
spi_transfer_reg(dev->spi,
AT86RF2XX_ACCESS_SRAM | AT86RF2XX_ACCESS_WRITE,
(char)offset, NULL);
spi_transfer_bytes(dev->spi, (char *)data, NULL, len);
gpio_set(dev->cs_pin);
spi_release(dev->spi);
}
int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length)
{
int trans_ret;
trans_ret = spi_transfer_byte(dev, reg, in);
if (trans_ret < 0) {
return -1;
}
trans_ret = spi_transfer_bytes(dev, out, in, length);
if (trans_ret < 0) {
return -1;
}
return trans_ret;
}
int ata8510_send_cmd(const ata8510_t *dev,
const uint8_t *tx_buffer,
const uint8_t *rx_buffer,
const size_t len)
{
int count;
spi_acquire(dev->params.spi);
gpio_clear(dev->params.cs_pin);
xtimer_usleep(1);
count = spi_transfer_bytes(
dev->params.spi, (char *)tx_buffer, (char *)rx_buffer, len
);
gpio_set(dev->params.cs_pin);
spi_release(dev->params.spi);
return count;
}
static int nvram_spi_write(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(dst);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
/* Re-assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_WRITE,
&addr.c[sizeof(addr.c) - spi_dev->address_count], NULL,
spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
return status;
}
static bool
spi_timeout_cb(void *data)
{
struct sol_spi *spi = data;
int ret;
spi_acquire(spi->bus);
gpio_clear(spi->cs_pin);
ret = spi_transfer_bytes(spi->bus, (char *)spi->transfer.tx,
(char *)spi->transfer.rx, spi->transfer.count);
gpio_set(spi->cs_pin);
spi_release(spi->bus);
spi->transfer.status = ret;
spi->transfer.timeout = NULL;
spi_transfer_dispatch(spi);
return false;
}
static int nvram_spi_write_9bit_addr(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
uint8_t cmd;
uint8_t addr;
cmd = NVRAM_SPI_CMD_WRITE;
/* The upper address bit is mixed into the command byte on certain devices,
* probably just to save a byte in the SPI transfer protocol. */
if (dst > 0xff) {
cmd |= 0x08;
}
/* LSB of address */
addr = (dst & 0xff);
spi_acquire(spi_dev->spi);
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_reg(spi_dev->spi, cmd, addr, NULL);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
gpio_set(spi_dev->cs);
spi_release(spi_dev->spi);
/* status contains the number of bytes actually written to the SPI bus. */
return status;
}
static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(src);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_READ,
&addr.c[sizeof(addr.c) - spi_dev->address_count],
NULL, spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
void at86rf231_spi_transfer(const uint8_t *data_out, uint8_t *data_in, uint16_t length)
{
spi_transfer_bytes(SPI_0, (char*)data_out, (char*)data_in, length);
}
int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length)
{
spi_transfer_byte(dev, reg, NULL);
return spi_transfer_bytes(dev, out, in, length);
}
static inline void enc_spi_transfer(encx24j600_t *dev, char *out, char *in, int len)
{
spi_transfer_bytes(dev->spi, dev->cs, false, out, in, len);
}
void at86rf2xx_fb_read(const at86rf2xx_t *dev,
uint8_t *data,
const size_t len)
{
spi_transfer_bytes(dev->spi, NULL, (char *)data, len);
}
int spi_transfer_byte(spi_t dev, char out, char *in)
{
return spi_transfer_bytes(dev, &out, in, 1);
}
static void cmdn(encx24j600_t *dev, uint8_t cmd, char *out, char *in, int len) {
spi_transfer_byte(dev->spi, dev->cs, true, cmd);
spi_transfer_bytes(dev->spi, dev->cs, false, out, in, len);
}