void c_main() { // Copy this core's experimental configuration from SDRAM load_config(); // Set up the core map spin1_application_core_map( system_width, system_height , (uint (*)[system_height])&core_map[0] ); // Accept packets freely from the network spin1_callback_on(MC_PACKET_RECEIVED, on_mc_packet_received, -1); // Set up timer spin1_set_timer_tick(config_root.tick_microseconds); spin1_callback_on(TIMER_TICK, on_timer_tick, 3); setup_router(); // Report that we're ready io_printf(IO_BUF, "Waiting for spin1_start barrier...\n"); // Run the experiment spin1_start(); cleanup_router(); store_results(); }
/****f* simple.c/c_main * * SUMMARY * This function is called at application start-up. * It is used to register event callbacks and begin the simulation. * * SYNOPSIS * int c_main() * * SOURCE */ void c_main() { io_printf (IO_STD, ">> simple\n"); /* get this core's IDs */ coreID = spin1_get_core_id(); chipID = spin1_get_chip_id(); /* TODO: Works on 4-chip board only! */ /* set the core map for the simulation */ if (NUMBER_OF_CHIPS > 0) core_map[0] = CORE_MAP_00; if (NUMBER_OF_CHIPS > 1) core_map[1] = CORE_MAP_01; if (NUMBER_OF_CHIPS > 2) core_map[2] = CORE_MAP_10; if (NUMBER_OF_CHIPS > 3) core_map[3] = CORE_MAP_11; spin1_set_core_map(NUMBER_OF_CHIPS, core_map); /* set timer tick value (in microseconds) */ spin1_set_timer_tick(TIMER_TICK_PERIOD); /* register callbacks */ spin1_callback_on(MC_PACKET_RECEIVED, count_packets, -1); spin1_callback_on(DMA_TRANSFER_DONE, check_memcopy, 0); spin1_callback_on(USER_EVENT, send_packets, 2); spin1_callback_on(TIMER_TICK, flip_led, 3); /* initialize application */ app_init(); /* go */ spin1_start(); /* report results */ app_done(); }
void c_main(void) { address_t address = system_load_sram(); if (!data_system(region_start(1, address)) || !data_get_output_keys(region_start(2, address)) || !input_filter_get_filters(&g_input, region_start(3, address)) || !input_filter_get_filter_routes(&g_input, region_start(4, address)) || !data_get_transform(region_start(5, address)) ) { io_printf(IO_BUF, "[Filter] Failed to initialise.\n"); return; } // Setup timer tick, start spin1_set_timer_tick(g_filter.machine_timestep); spin1_callback_on(MCPL_PACKET_RECEIVED, mcpl_callback, -1); spin1_callback_on(TIMER_TICK, filter_update, 2); while (true) { // Wait for data loading, etc. event_wait(); // Determine how long to simulate for config_get_n_ticks(); // Perform the simulation spin1_start(SYNC_WAIT); } }
void c_main (void) { uint coreID = spin1_get_core_id(); uint chipID = spin1_get_chip_id(); if(chipID == 0 && coreID == 1) { io_printf (IO_STD, "Hello world! (via SDP)\n"); io_printf (IO_BUF, "Hello world! (via the terminal)\n"); if(spin_devin_init() == 0) { io_printf(IO_BUF, "Error: could not connect to the SpiNNaker!\n"); } spin_devin_send_motor(2000 << 16 | 2000); uint cam = spin_devin_get_camera(); io_printf(IO_BUF, "camera: %08x\n", cam); spin1_set_timer_tick(10000); spin1_callback_on(TIMER_TICK, upd, 0); spin_devin_dispose(); } spin1_start(); }
// Entry point void c_main(void) { // Initialise uint32_t timer_period = 0; if (!initialize(&timer_period)) { log_error("Error in initialisation - exiting!"); rt_error(RTE_SWERR); } // Initialise the incoming spike buffer if (!in_spikes_initialize_spike_buffer(8192)) { return; } // Set timer_callback spin1_set_timer_tick(timer_period); // Register callbacks spin1_callback_on(MC_PACKET_RECEIVED, incoming_spike_callback, MC); spin1_callback_on(TIMER_TICK, timer_callback, TIMER); // Start the time at "-1" so that the first tick will be 0 time = UINT32_MAX; simulation_run(timer_callback, TIMER); }
//! \brief The entry point for this model. void c_main(void) { // Load DTCM data uint32_t timer_period; // initialise the model if (!initialise(&timer_period)){ rt_error(RTE_API); } // Start the time at "-1" so that the first tick will be 0 time = UINT32_MAX; // Set timer tick (in microseconds) log_info("setting timer tick callback for %d microseconds", timer_period); spin1_set_timer_tick(timer_period); // Set up the timer tick callback (others are handled elsewhere) spin1_callback_on(TIMER_TICK, timer_callback, TIMER_AND_BUFFERING); // Set up callback listening to SDP messages simulation_register_simulation_sdp_callback( &simulation_ticks, &infinite_run, SDP_AND_DMA_AND_USER); // set up provenance registration simulation_register_provenance_callback( c_main_store_provenance_data, PROVENANCE_DATA_REGION); simulation_run(); }
/****f* main.c/c_main * * SUMMARY * This function is called at application start-up. The application programmer * must implement the function body to configure hardware, register callbacks, * and finally begin the simulation. * * SYNOPSIS * int c_main() * * SOURCE */ void c_main() { io_printf(IO_STD, "Hello, World!\nBooting application...\n"); // Set the number of chips in the simulation spin1_set_core_map(64, (uint *)(0x74220000)); // FIXME make the number of chips dynamic // Set timer tick (in microseconds) spin1_set_timer_tick(1000*1); // Configure simulation load_application_data(); load_mc_routing_tables(); configure_app_frame(); #ifdef STDP load_stdp_config_data(); alloc_stdp_post_TS_mem(); #endif // Register callbacks spin1_callback_on(DMA_TRANSFER_DONE, dma_callback, 0); spin1_callback_on(TIMER_TICK, timer_callback, 2); spin1_callback_on(SDP_PACKET_RX, sdp_packet_callback, 1); // Go! // scheduling a callback at t=0 to evaluate the first time step spin1_schedule_callback(timer_callback, 0, 0, 2); io_printf(IO_STD, "Application booted!\nStarting simulation...\n"); spin1_start(); }
void c_main(void) { // Load in all data address_t address = system_load_sram(); if (!get_packets(region_start(2, address), &start_packets) || !get_packets(region_start(4, address), &end_packets) ) { return; } spin1_set_timer_tick(1000); spin1_callback_on(TIMER_TICK, tick, 2); while(true) { // Wait for data loading, etc. event_wait(); // Determine how long to simulate for config_get_n_ticks(); // Transmit all packets assigned to be sent prior to the start of the // simulation transmit_packet_region(start_packets); // Synchronise with the simulation spin1_start(SYNC_WAIT); } }
// Entry point void c_main(void) { // Initialise uint32_t timer_period = 0; if (!initialize(&timer_period)) { log_error("Error in initialisation - exiting!"); rt_error(RTE_SWERR); } // Start the time at "-1" so that the first tick will be 0 time = UINT32_MAX; // Initialize the incoming spike buffer if (!in_spikes_initialize_spike_buffer(256)) { rt_error(RTE_SWERR); } // Set timer tick (in microseconds) spin1_set_timer_tick(timer_period); // Register callbacks spin1_callback_on(MC_PACKET_RECEIVED, incoming_spike_callback, -1); spin1_callback_on(USER_EVENT, spike_process, 1); spin1_callback_on(TIMER_TICK, timer_callback, 2); log_info("Starting"); simulation_run(); }
void c_main() { // Set up timer to tick once per ms spin1_set_timer_tick(10); spin1_callback_on(TIMER_TICK, on_timer_tick, 3); // Go! spin1_start(); }
void init_Handlers() { spin1_callback_on(SDP_PACKET_RX, hSDP, SCP_PRIORITY_VAL); spin1_callback_on(MCPL_PACKET_RECEIVED, hMCPL, MCPL_PRIORITY_VAL); spin1_set_timer_tick(TIMER_TICK_PERIOD_US); spin1_callback_on(TIMER_TICK, hTimer, TIMER_PRIORITY_VAL); spin1_callback_on(USER_EVENT, collectData, SCHEDULED_PRIORITY_VAL); init_sdp_container(); //initIPTag(); --> replaced with initiateIPTagReading() spin1_schedule_callback(initiateIPTagReading, 0, 0, 1); }
// The idea is to set a communication system whose purpose // is to exchange data from a virtual master node (situated // at core 0, chip 0) and all the other cores situated on all // the other chips. From master node to other nodes we use multicast // messages, whereas from a node to master node we use sdp messages. void c_main (void) { // simulation initialization coreID = spin1_get_core_id(); chipID = spin1_get_chip_id(); if(chipID == 0 && coreID == 1) { io_printf(IO_BUF,"CoreID is %u, ChipID is %u\n",coreID, chipID); spin1_set_timer_tick(TICK_TIME); // end of simulation initialization spin1_callback_on(TIMER_TICK, update, 1); spin_devin_init(); } spin1_start(); }
void c_main(void) { address_t address = system_load_sram(); if (!data_system(region_start(1, address)) || !data_get_output_keys(region_start(2, address)) || !input_filter_get_filters(&g_input, region_start(3, address)) || !input_filter_get_filter_routes(&g_input, region_start(4, address)) || !data_get_transform(region_start(5, address)) ) { io_printf(IO_BUF, "[Filter] Failed to initialise.\n"); return; } // Set up routing tables if(leadAp) { system_lead_app_configured(); } // Setup timer tick, start spin1_set_timer_tick(g_filter.machine_timestep); spin1_callback_on(MCPL_PACKET_RECEIVED, mcpl_callback, -1); spin1_callback_on(TIMER_TICK, filter_update, 2); spin1_start(SYNC_WAIT); }
void c_main (void) { io_printf (IO_STD, "Starting communication test.\n"); // get this core's ID coreID = spin1_get_core_id(); chipID = spin1_get_chip_id(); // get this chip's coordinates for core map my_x = chipID >> 8; my_y = chipID & 0xff; my_chip = (my_x * NUMBER_OF_YCHIPS) + my_y; // operate only if in core map! if ((core_map[my_x][my_y] & (1 << coreID)) == 0) { io_printf (IO_STD, "Stopping comm. (Not in core map)\n"); return; } // set the core map for the simulation spin1_application_core_map(NUMBER_OF_XCHIPS, NUMBER_OF_YCHIPS, core_map); spin1_set_timer_tick (TIMER_TICK_PERIOD); // register callbacks spin1_callback_on (MC_PACKET_RECEIVED, receive_data, 0); spin1_callback_on (TIMER_TICK, update, 0); spin1_callback_on (SDP_PACKET_RX, host_data, 0); // Initialize routing tables routing_table_init (); // Initialize SDP message buffer sdp_init (); // go spin1_start(); }
//! \brief The entry point for this model. void c_main(void) { // Load DTCM data uint32_t timer_period; // initialise the model if (!initialize(&timer_period)){ rt_error(RTE_API); } // Start the time at "-1" so that the first tick will be 0 time = UINT32_MAX; // Set timer tick (in microseconds) log_info("setting timer tic callback for %d microseconds", timer_period); spin1_set_timer_tick(timer_period); // Set up the timer tick callback (others are handled elsewhere) spin1_callback_on(TIMER_TICK, timer_callback, 2); log_info("Starting"); simulation_run(); }
void c_main (void) { int chipIDs[] = {0, 1, 256, 257}; chipID = spin1_get_chip_id(); coreID = spin1_get_core_id(); spikeNumber = 0; //io_printf(IO_STD, "Simulation starting on (chip: %d, core: %d)...\n", chipID, coreID); // Set the number of chips in the simulation //spin1_set_core_map(64, (uint *)(0x74220000)); // set the core map for the simulation //spin1_application_core_map(2, 2, core_map); //spin1_set_core_map(4, (uint *)(core_map)); // initialise routing entries // set a MC routing table entry to send my packets back to me if (chipID == 0 && coreID == 1) { /* ------------------------------------------------------------------- */ /* initialise routing entries */ /* ------------------------------------------------------------------- */ /* set a MC routing table entry to send my packets back to me */ io_printf(IO_STD, "Setting routing table on (chip: %d, core: %d)...\n", chipID, coreID); uint e = rtr_alloc (1); if (e == 0) rt_error (RTE_ABORT); rtr_mc_set (e, // entry 0x11100001, // key 0xFFFF0001, // mask SOUTH_WEST ); e = rtr_alloc (1); if (e == 0) rt_error (RTE_ABORT); rtr_mc_set (e, // entry 0x11100000, // key 0xFFFF0001, // mask SOUTH_WEST ); e = rtr_alloc (1); if (e == 0) rt_error (RTE_ABORT); rtr_mc_set (e, 0x80000000 | 9 << 7 | 0 << 2, 0x80000000 | 15 << 7 | 31 << 2, CORE(2) // core 2 handles bump sensor ); e = rtr_alloc (1); if (e == 0) rt_error (RTE_ABORT); rtr_mc_set (e, 0x80000000 | 9 << 7 | 4 << 2 | 2, 0x80000000 | 15 << 7 | 31 << 2 | 3, CORE(3) // core 3 handles compass sensor ); e = rtr_alloc (1); if (e == 0) rt_error (RTE_ABORT); rtr_mc_set (e, 0x80000000 , //| 9 << 7 | 0 << 2, 0x80000000 , //| 15 << 7 | 0 << 2, CORE(4) // core 4 logs data ); } // Call hardware and simulation configuration functions spin1_set_timer_tick(TIME_STEP_MICROSEC); if (chipID == 0 && coreID == 1) //core1 handles time-based stuff { spin1_callback_on(TIMER_TICK, timer_callback, TIMER_PRIORITY); } if (chipID == 0 && coreID == 2) { spin1_callback_on(MCPL_PACKET_RECEIVED, bump_received, MC_PACKET_EVENT_PRIORITY); } if (chipID == 0 && coreID == 3) { spin1_callback_on(MC_PACKET_RECEIVED, enable_packet_received, MC_PACKET_EVENT_PRIORITY); } if (chipID == 0 && coreID == 4) { // Register callbacks spin1_callback_on(MC_PACKET_RECEIVED, multiCastPacketReceived_callback, MC_PACKET_EVENT_PRIORITY); spin1_callback_on(MCPL_PACKET_RECEIVED, multiCastPacketReceived_with_payload_callback, MC_PACKET_EVENT_PRIORITY); } // transfer control to the run-time kernel //if (chipID == 0 && coreID == 1) { spin1_start(0); } }
void c_main (void) { // simulation initialization coreID = spin1_get_core_id(); chipID = spin1_get_chip_id(); spin1_set_timer_tick(TICK_TIME); // the intrachip communication is totally independent from a // chip to another. chips do not interfere with each other (good point) if(chipID == 0) { // 0, 0 // in this chip, we test master to nodes, then nodes to master // results: performance is good // from master to nodes spin1_set_mc_table_entry(0x6, ERROR_MSG, 0xFFFFFFFF, ALL_NODES_MASTER_CHIP); // froms nodes to master spin1_set_mc_table_entry(0x7, UPD_MSG, 0xFFFFFFFF, MASTER_CORE); if(coreID == 1) { // master core // events setting spin1_callback_on(MC_PACKET_RECEIVED,eventMaster_chip0,0); spin1_callback_on(TIMER_TICK, update_chip0, 0); } else { // nodes // events setting spin1_callback_on(MC_PACKET_RECEIVED,eventNode_chip0,0); } } else if(chipID == 1) { // 0, 1 // in this chip, we test parallel message sending (core 1 to 2, core 3 to 4 and core 5 to 6, independently) // results: performance good spin1_set_mc_table_entry(0x2, 0x2, 0xFFFFFFFF, CORE(2)); spin1_set_mc_table_entry(0x4, 0x4, 0xFFFFFFFF, CORE(4)); spin1_set_mc_table_entry(0x6, 0x6, 0xFFFFFFFF, CORE(6)); if(coreID == 3 | coreID == 1 | coreID == 5) { // sending cores spin1_callback_on(TIMER_TICK, update_chip1, -2); } else { // receiving cores spin1_callback_on(MC_PACKET_RECEIVED,eventRec_chip1,-1); } } else if(chipID == 256) { // 1, 0 // ... } else if(chipID == 257) { // 1, 1 // ... } // Note that calling io_printf in the functions slows down a lot the system. // Therefore tests should be performed without calling this function // (or calling it not so often) spin1_start(); }
void c_main(void) { // Set the system up io_printf(IO_BUF, "[Ensemble] C_MAIN\n"); address_t address = system_load_sram(); if (!data_system(region_start(1, address))) { io_printf(IO_BUF, "[Ensemble] Failed to start.\n"); return; } // Get data data_get_bias(region_start(2, address), g_ensemble.n_neurons); data_get_encoders(region_start(3, address), g_ensemble.n_neurons, g_input.n_dimensions); data_get_decoders(region_start(4, address), g_ensemble.n_neurons, g_n_output_dimensions); data_get_keys(region_start(5, address), g_n_output_dimensions); // Get the inhibitory gains g_ensemble.inhib_gain = spin1_malloc(g_ensemble.n_neurons * sizeof(value_t)); if (g_ensemble.inhib_gain == NULL) { io_printf(IO_BUF, "[Ensemble] Failed to malloc inhib gains.\n"); return; } spin1_memcpy(g_ensemble.inhib_gain, region_start(10, address), g_ensemble.n_neurons * sizeof(value_t)); for (uint n = 0; n < g_ensemble.n_neurons; n++) { io_printf(IO_BUF, "Inhib gain[%d] = %k\n", n, g_ensemble.inhib_gain[n]); } // Load subcomponents if (!input_filter_get_filters(&g_input, region_start(6, address)) || !input_filter_get_filter_routes(&g_input, region_start(7, address)) || !input_filter_get_filters(&g_input_inhibitory, region_start(8, address)) || !input_filter_get_filter_routes(&g_input_inhibitory, region_start(9, address)) || !input_filter_get_filters(&g_input_modulatory, region_start(11, address)) || !input_filter_get_filter_routes(&g_input_modulatory, region_start(12, address))) { io_printf(IO_BUF, "[Ensemble] Failed to start.\n"); return; } if(!get_pes(region_start(13, address))) { io_printf(IO_BUF, "[Ensemble] Failed to start.\n"); return; } // Set up recording if (!record_buffer_initialise(&g_ensemble.recd, region_start(15, address), simulation_ticks, g_ensemble.n_neurons)) { io_printf(IO_BUF, "[Ensemble] Failed to start.\n"); return; } // Set up routing tables io_printf(IO_BUF, "[Ensemble] C_MAIN Configuring system.\n"); if(leadAp){ system_lead_app_configured(); } // Setup timer tick, start io_printf(IO_BUF, "[Ensemble] C_MAIN Set timer and spin1_start.\n"); spin1_set_timer_tick(g_ensemble.machine_timestep); spin1_start(SYNC_WAIT); }