void omap_temp_sensor_check(void) { u32 temp; /* Set the counter to 1 ms */ sr32(CORE_BANDGAP_COUNTER, BGAP_COUNTER_START_BIT, BGAP_COUNTER_NUM_BITS, BGAP_COUNTER_VALUE); /* Enable continuous mode. */ sr32(CORE_BANDGAP_CTRL, BGAP_SINGLE_MODE_START_BIT, BGAP_SINGLE_MODE_NUM_BITS, BGAP_CONTINUOUS_MODE); /* Wait till the first conversion is done wait for at least 1ms */ spin_delay(20000); /* Read the temperature adc_value */ temp = readl(CORE_TEMP_SENSOR); temp = temp & BGAP_TEMP_SENSOR_DTEMP_MASK; /* If the samples are untrimmed divide by 1.2 */ if (readl(STD_FUSE_OPP_BGAP) == 0) temp = temp * 5 / 6; /* * Compare with TSHUT high temperature. If high ask the * user to shut down and restart after sometime else * Disable continuous mode. */ if (temp < TSHUT_HIGH_ADC_CODE) { /* Disable contiuous mode */ sr32(CORE_BANDGAP_CTRL, BGAP_SINGLE_MODE_START_BIT, BGAP_SINGLE_MODE_NUM_BITS, ~BGAP_CONTINUOUS_MODE); } else { printf("OMAP chip temperature is too high!!!\n"); printf("Please power off and try booting after sometime\n"); /* Bypass MPU, CORE, IVA, PER, ABE, USB DPLLs */ sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_FAST_RELOCK_BYPASS); wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); while (1); } }
int main(void) { int i,time; cprintf("priority process will sleep %d ticks\n",SLEEP_TIME); sleep(SLEEP_TIME); memset(pids, 0, sizeof(pids)); lab6_set_priority(TOTAL + 1); for (i = 0; i < TOTAL; i ++) { acc[i]=0; if ((pids[i] = fork()) == 0) { lab6_set_priority(i + 1); acc[i] = 0; while (1) { spin_delay(); ++ acc[i]; if(acc[i]%4000==0) { if((time=gettime_msec())>MAX_TIME) { cprintf("child pid %d, acc %d, time %d\n",getpid(),acc[i],time); exit(acc[i]); } } } } if (pids[i] < 0) { goto failed; } } cprintf("main: fork ok,now need to wait pids.\n"); for (i = 0; i < TOTAL; i ++) { status[i]=0; waitpid(pids[i],&status[i]); cprintf("main: pid %d, acc %d, time %d\n",pids[i],status[i],gettime_msec()); } cprintf("main: wait pids over\n"); cprintf("stride sched correct result:"); for (i = 0; i < TOTAL; i ++) { cprintf(" %d", (status[i] * 2 / status[0] + 1) / 2); } cprintf("\n"); return 0; failed: for (i = 0; i < TOTAL; i ++) { if (pids[i] > 0) { kill(pids[i]); } } panic("FAIL: T.T\n"); }
/* TODO: FREQ update method is not working so shadow registers programming * is just for same of completeness. This would be safer if auto * trasnitions are working */ void emif_config(unsigned int base, const struct ddr_regs *ddr_regs) { unsigned int reg_value, rev; rev = omap_revision(); /* * set SDRAM CONFIG register * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8 */ writel(readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xBFFFFFFF, base + EMIF_LPDDR2_NVM_CONFIG); writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG); /* PHY control values */ writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1); writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW); /* * EMIF_READ_IDLE_CTRL */ writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL); writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL_SHDW); /* * EMIF_SDRAM_TIM_1 */ writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1); writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW); /* * EMIF_SDRAM_TIM_2 */ writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2); writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW); /* * EMIF_SDRAM_TIM_3 */ writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3); writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW); /* * EMIF_PWR_MGMT_CTRL */ /* * poll MR0 register (DAI bit) * REG_CS[31] = 0 -- Mode register command to CS0 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW */ writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); do { reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA); } while ((reg_value & 0x1) != 0); writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); do { reg_value = readl(base + EMIF_LPDDR2_MODE_REG_DATA); } while ((reg_value & 0x1) != 0); /* set MR10 register */ writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA); /* wait for tZQINIT=1us */ spin_delay(2000); /* value for up to 2GHz MPU spin */ writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA); /* wait for tZQINIT=1us */ spin_delay(2000); /* value for up to 2GHz MPU spin */ writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG); /* set MR1 register */ writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA); writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA); /* set MR2 register RL=6 for OPP100 */ writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG); writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA); writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG); writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA); /* Set SDRAM CONFIG register again here with final RL-WL value */ writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG); writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1); /* * EMIF_SDRAM_REF_CTRL * refresh rate = DDR_CLK / reg_refresh_rate * 3.9 uS = (400MHz) / reg_refresh_rate */ writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL); writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW); /* set MR16 register */ writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG); writel(0, base + EMIF_LPDDR2_MODE_REG_DATA); writel(CS1_MR(MR16_ADDR | REF_EN), base + EMIF_LPDDR2_MODE_REG_CFG); writel(0, base + EMIF_LPDDR2_MODE_REG_DATA); /* LPDDR2 init complete */ }
/***************************************** * Routine: ddr_init * Description: Configure DDR * EMIF1 -- CS0 -- DDR1 (256 MB) * EMIF2 -- CS0 -- DDR2 (256 MB) *****************************************/ void do_ddr_init(const struct ddr_regs *emif1_ddr_regs, const struct ddr_regs *emif2_ddr_regs) { unsigned int rev; rev = omap_revision(); if (rev == OMAP4430_ES1_0) { /* Configure the Control Module DDRIO device */ __raw_writel(0x1c1c1c1c, 0x4A100638); __raw_writel(0x1c1c1c1c, 0x4A10063c); __raw_writel(0x1c1c1c1c, 0x4A100640); __raw_writel(0x1c1c1c1c, 0x4A100648); __raw_writel(0x1c1c1c1c, 0x4A10064c); __raw_writel(0x1c1c1c1c, 0x4A100650); /* LPDDR2IO set to NMOS PTV */ __raw_writel(0x00ffc000, 0x4A100704); } else if (rev == OMAP4430_ES2_0) { __raw_writel(0x9e9e9e9e, 0x4A100638); __raw_writel(0x9e9e9e9e, 0x4A10063c); __raw_writel(0x9e9e9e9e, 0x4A100640); __raw_writel(0x9e9e9e9e, 0x4A100648); __raw_writel(0x9e9e9e9e, 0x4A10064c); __raw_writel(0x9e9e9e9e, 0x4A100650); /* LPDDR2IO set to NMOS PTV */ __raw_writel(0x00ffc000, 0x4A100704); } else if (rev >= OMAP4430_ES2_1) { __raw_writel(0x7c7c7c7c, 0x4A100638); __raw_writel(0x7c7c7c7c, 0x4A10063c); __raw_writel(0x7c787c00, 0x4A100640); __raw_writel(0x7c7c7c7c, 0x4A100648); __raw_writel(0x7c7c7c7c, 0x4A10064c); __raw_writel(0x7c787c00, 0x4A100650); /* * Adjust Internal Vref controls to reduce leakage * for chip retention (Core OSWR) */ __raw_writel(0xa388bc03, 0x4A100644); __raw_writel(0xa388bc03, 0x4A100654); /* LPDDR2IO set to NMOS PTV */ /* To be updated according to Process */ /*__raw_writel(0x00ffc000, 0x4A100704); */ } /* DDR needs to be initialised @ 19.2 MHz * So put core DPLL in bypass mode * Configure the Core DPLL but don't lock it */ configure_core_dpll_no_lock(); /* No IDLE: BUG in SDC */ __raw_writel(0x0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL); __raw_writel(0x0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL); /* Configure EMIF1 */ emif_config(EMIF1_BASE, emif1_ddr_regs); /* Configure EMIF2 */ emif_config(EMIF2_BASE, emif2_ddr_regs); /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ lock_core_dpll_shadow(); /* TODO: SDC needs few hacks to get DDR freq update working */ /* Set DLL_OVERRIDE = 0 */ __raw_writel(0x0, CM_DLL_CTRL); spin_delay(200); /* Check for DDR PHY ready for EMIF1 & EMIF2 */ while(((__raw_readl(EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04) || ((__raw_readl(EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04)); /* Reprogram the DDR PYHY Control register */ /* PHY control values */ sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); /* Put the Core Subsystem PD to ON State */ /* No IDLE: BUG in SDC */ __raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL); __raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL); /* SYSTEM BUG: * In n a specific situation, the OCP interface between the DMM and * EMIF may hang. * 1. A TILER port is used to perform 2D burst writes of * width 1 and height 8 * 2. ELLAn port is used to perform reads * 3. All accesses are routed to the same EMIF controller * * Work around to avoid this issue REG_SYS_THRESH_MAX value should * be kept higher than default 0x7. As per recommondation 0x0A will * be used for better performance with REG_LL_THRESH_MAX = 0x00 */ if (omap_revision() >= OMAP4460_ES1_0) { __raw_writel(0x0A300000, EMIF1_BASE + EMIF_L3_CONFIG); __raw_writel(0x0A300000, EMIF2_BASE + EMIF_L3_CONFIG); } else { __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG); __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG); } reset_phy(EMIF1_BASE); reset_phy(EMIF2_BASE); }