void board_init_f(ulong dummy) { dcache_disable(); socfpga_init_security_policies(); socfpga_sdram_remap_zero(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); socfpga_watchdog_disable(); spl_early_init(); /* Configure the clock based on handoff */ cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG /* release osc1 watchdog timer 0 from reset */ socfpga_reset_deassert_osc1wd0(); /* reconfigure and enable the watchdog */ hw_watchdog_init(); WATCHDOG_RESET(); #endif /* CONFIG_HW_WATCHDOG */ config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* Set up our preloader console */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { pr_err("%s: pinctrl init failed: %d\n", __func__, ret); hang(); } ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); if (ret) { pr_err("%s: failed to set up console UART\n", __func__); hang(); } preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; struct rk3399_pmusgrf_regs *sgrf; struct rk3399_grf_regs *grf; int ret; #define EARLY_UART #ifdef EARLY_UART /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printascii("U-Boot SPL board init"); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* * Disable DDR and SRAM security regions. * * As we are entered from the BootROM, the region from * 0x0 through 0xfffff (i.e. the first MB of memory) will * be protected. This will cause issues with the DW_MMC * driver, which tries to DMA from/to the stack (likely) * located in this range. */ sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); rk_clrreg(&sgrf->slv_secure_con4, 0x2000); /* eMMC clock generator: disable the clock multipilier */ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); rk_clrreg(&grf->emmccore_con[11], 0x0ff); secure_timer_init(); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { int ret; ret = spl_early_init(); if (ret) { printf("spl_early_init() failed: %d\n", ret); hang(); } preloader_console_init(); /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); }
void board_init_f(ulong dummy) { struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ /* Enable early UART on the RK3288 */ struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { struct udevice *dev; int ret; arch_cpu_init(); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = uclass_get_device(UCLASS_CLK, 0, &dev); if (ret) { debug("Clock init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RESET, 0, &dev); if (ret) { debug("Reset init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); if (ret) { debug("%s: Cannot find pinctrl device\n", __func__); return; } /* enable console uart printing */ preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void early_system_init(void) { /* * The ROM will only have set up sufficient pinmux to allow for the * first 4KiB NOR to be read, we must finish doing what we know of * the NOR mux in this space in order to continue. */ #ifdef CONFIG_NOR_BOOT enable_norboot_pin_mux(); #endif watchdog_disable(); set_uart_mux_conf(); setup_early_clocks(); uart_soft_reset(); #ifdef CONFIG_SPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ save_omap_boot_params(); #endif #ifdef CONFIG_DEBUG_UART_OMAP debug_uart_init(); #endif #ifdef CONFIG_SPL_BUILD spl_early_init(); #endif #ifdef CONFIG_TI_I2C_BOARD_DETECT do_board_detect(); #endif #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); #endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; struct rk3188_pmu *pmu; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } /* * Recover the bootrom's stackpointer. * For whatever reason needs to run after rockchip_get_clk. */ pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); if (IS_ERR(pmu)) error("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif }
void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); unsigned long sdram_size; unsigned long reg; int ret; /* * First C code to run. Clear fake OCRAM ECC first as SBE * and DBE might triggered during power on */ reg = readl(&sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_SERR) writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); if (reg & SYSMGR_ECC_OCRAM_DERR) writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, &sysmgr_regs->eccgrp_ocram); memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); if (!socfpga_is_booting_from_fpga()) { /* Put FPGA bridges into reset too. */ socfpga_bridges_reset(1); } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); timer_init(); debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ if (cm_basic_init(cm_default_cfg)) hang(); /* Enable bootrom to configure IOs. */ sysmgr_config_warmrstcfgio(1); /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); sysmgr_config_warmrstcfgio(0); /* configure the pin muxing through system manager */ sysmgr_config_warmrstcfgio(1); sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); /* De-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); socfpga_bridges_reset(0); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ sys_mgr_frzctrl_thaw_req(); #ifdef CONFIG_DEBUG_UART socfpga_per_reset(SOCFPGA_RESET(UART0), 0); debug_uart_init(); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* enable console uart printing */ preloader_console_init(); if (sdram_mmr_init_full(0xffffffff) != 0) { puts("SDRAM init failed.\n"); hang(); } debug("SDRAM: Calibrating PHY\n"); /* SDRAM calibration */ if (sdram_calibration_full() == 0) { puts("SDRAM calibration failed.\n"); hang(); } sdram_size = sdram_calculate_size(); debug("SDRAM: %ld MiB\n", sdram_size >> 20); /* Sanity check ensure correct SDRAM size specified */ if (get_ram_size(0, sdram_size) != sdram_size) { puts("SDRAM size check failed!\n"); hang(); } if (!socfpga_is_booting_from_fpga()) socfpga_bridges_reset(1); }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; /* Example code showing how to enable the debug UART on RK3288 */ #include <asm/arch/grf_rk3288.h> /* Enable early UART on the RK3288 */ #define GRF_BASE 0xff770000 struct rk3288_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | GPIO7C6_MASK << GPIO7C6_SHIFT, GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } rockchip_timer_init(); configure_l2ctlr(); ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } #if !defined(CONFIG_SPL_OF_PLATDATA) if (of_machine_is_compatible("phytec,rk3288-phycore-som")) { ret = phycore_init(); if (ret) { debug("Failed to set up phycore power settings: %d\n", ret); return; } } #endif #if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } #endif #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }
void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; int ret; /* Example code showing how to enable the debug UART on RK3188 */ #ifdef EARLY_UART #include <asm/arch/grf_rk3188.h> /* Enable early UART on the RK3188 */ #define GRF_BASE 0x20008000 struct rk3188_grf * const grf = (void *)GRF_BASE; rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B1_MASK << GPIO1B1_SHIFT | GPIO1B0_MASK << GPIO1B0_SHIFT, GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ debug_uart_init(); printch('s'); printch('p'); printch('l'); printch('\n'); #endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("Pinctrl init failed: %d\n", ret); return; } ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } setup_arm_clock(); #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(BROM_BOOT_NEXTSTAGE); #endif }