void irq_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
    unsigned long map = *cpus_addr(*mask);
    int satt, cpu, cpu_bmask;
    u32 val;

    satt = 1 << 15;

    /* 
     * NoteXXX: CPU1 SGI is configured as secure as default.
     *          Need to use the secure SGI 1 which is for waking up cpu1.
     */
    if (irq == CPU_BRINGUP_SGI)
    {
        if (irq_total_secondary_cpus)
        {
            --irq_total_secondary_cpus;
            satt = 0;
        }
    }
    
    val = readl(GIC_ICDISR + 4 * (irq / 32));
    if (!(val & (1 << (irq % 32)))) {   /*  secure interrupt? */
        satt = 0;
    }

    cpu = 0;
    cpu_bmask = 0;

#if defined(SPM_MCDI_FUNC)
    /*
     * Processors cannot receive interrupts during power-down.
     * Wait until the SPM checks status and returns. 
     */
    for_each_cpu(cpu, mask) {
        cpu_bmask |= 1 << cpu;
    }
    spm_check_core_status_before(cpu_bmask);
#endif

    /*
     * Ensure that stores to Normal memory are visible to the
     * other CPUs before issuing the IPI.
     */
    dsb();
    *(volatile u32 *)(GIC_DIST_BASE + 0xf00) = (map << 16) | satt | irq;
    dsb();

#if defined(SPM_MCDI_FUNC)
    spm_check_core_status_after(cpu_bmask);
#endif

}
static inline int mcidle_handler(int cpu)
{

#if 1
    if (idle_switch[IDLE_TYPE_MC]) {
        if (mcidle_can_enter(cpu)) {
            go_to_mcidle(cpu);
            //go_to_soidle(0,cpu);
            return 1;
        }
    }
#else

    if (idle_switch[IDLE_TYPE_MC]) {
        mtk_wdt_suspend();
        for(;;)
        {
            if(cpu==1)
            {
                printk("MCDI start\n");
                spm_go_to_mcdi_ipi_test(cpu);
                printk("MCDI %s\n",spm_get_wake_up_result(SPM_PCM_SODI));
            }
            if(cpu==0)
            {


#if 1

                if(spm_read(SPM_FC1_PWR_CON)==0x32)
                {
                    //printk("IPI start\n");
                    spm_check_core_status_before(2);
                    //printk("1. SPM_PCM_EVENT_VECTOR2 = 0x%x, SPM_PCM_REG15_DATA = 0x%x \n", spm_read(SPM_PCM_EVENT_VECTOR2),spm_read(SPM_PCM_REG15_DATA));
                    //mdelay(1);
                    spm_check_core_status_after(2);
                    //printk("2. SPM_PCM_EVENT_VECTOR2 = 0x%x, SPM_PCM_REG15_DATA = 0x%x \n", spm_read(SPM_PCM_EVENT_VECTOR2),spm_read(SPM_PCM_REG15_DATA));
                }
#endif

            }
        }
    }

#endif
    return 0;
}