static int
qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
{
int rc;
struct qpnp_pon_config *cfg = NULL;
u8 pon_rt_sts = 0, pon_rt_bit = 0;
cfg = qpnp_get_cfg(pon, pon_type);
if (!cfg)
return -EINVAL;
/* Check if key reporting is supported */
if (!cfg->key_code)
return 0;
/* check the RT status to get the current status of the line */
rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
QPNP_PON_RT_STS(pon->base), &pon_rt_sts, 1);
if (rc) {
dev_err(&pon->spmi->dev, "Unable to read PON RT status\n");
return rc;
}
switch (cfg->pon_type) {
case PON_KPDPWR:
pon_rt_bit = QPNP_PON_KPDPWR_N_SET;
break;
case PON_RESIN:
pon_rt_bit = QPNP_PON_RESIN_N_SET;
break;
case PON_CBLPWR:
pon_rt_bit = QPNP_PON_CBLPWR_N_SET;
break;
default:
return -EINVAL;
}
input_report_key(pon->pon_input, cfg->key_code,
(pon_rt_sts & pon_rt_bit));
input_sync(pon->pon_input);
#ifdef CONFIG_MACH_MONTBLANC
if((cfg->key_code == 107) && (pon_rt_sts & pon_rt_bit)){
pon->powerkey_state = 1;
}else if((cfg->key_code == 107) && !(pon_rt_sts & pon_rt_bit)){
pon->powerkey_state = 0;
}
#else
if((cfg->key_code == 116) && (pon_rt_sts & pon_rt_bit)){
pon->powerkey_state = 1;
}else if((cfg->key_code == 116) && !(pon_rt_sts & pon_rt_bit)){
pon->powerkey_state = 0;
}
#endif
#if CONFIG_SEC_DEBUG
#ifdef CONFIG_MACH_MONTBLANC
sec_debug_check_crash_key(116, pon->powerkey_state);
#else
sec_debug_check_crash_key(cfg->key_code, pon->powerkey_state);
#endif
#endif
#if defined(CONFIG_MACH_MONTBLANC)
check_pkey_press=pon->powerkey_state;
#endif
return 0;
}
static int qpnp_iadc_rds_trim_update_check(struct qpnp_iadc_chip *iadc)
{
int rc = 0;
u8 trim2_val = 0, smbb_batt_trm_data = 0;
u8 smbb_batt_trm_cnst_rds = 0;
if (!iadc->rds_trim_default_check) {
pr_debug("No internal rds trim check needed\n");
return 0;
}
rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_NOMINAL_RSENSE, &trim2_val);
if (rc < 0) {
pr_err("qpnp adc trim2_fullscale1 reg read failed %d\n", rc);
return rc;
}
rc = spmi_ext_register_readl(iadc->adc->spmi->ctrl, iadc->adc->slave,
iadc->batt_id_trim_cnst_rds, &smbb_batt_trm_data, 1);
if (rc < 0) {
pr_err("batt_id trim_cnst rds reg read failed %d\n", rc);
return rc;
}
smbb_batt_trm_cnst_rds = smbb_batt_trm_data &
SMBB_BAT_IF_TRIM_CNST_RDS_MASK;
pr_debug("n_trim:0x%x smb_trm:0x%x\n", trim2_val, smbb_batt_trm_data);
if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEA) {
if ((smbb_batt_trm_cnst_rds ==
SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) &&
(trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) {
iadc->rsense_workaround_value =
QPNP_IADC_RSENSE_DEFAULT_VALUE;
iadc->default_internal_rsense = true;
}
} else if (iadc->rds_trim_default_type ==
QPNP_IADC_RDS_DEFAULT_TYPEB) {
if ((smbb_batt_trm_cnst_rds >=
SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) &&
(trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) {
iadc->rsense_workaround_value =
QPNP_IADC_RSENSE_DEFAULT_VALUE;
iadc->default_internal_rsense = true;
} else if ((smbb_batt_trm_cnst_rds <
SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) &&
(trim2_val ==
QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) {
if (iadc->iadc_comp.id == COMP_ID_GF) {
iadc->rsense_workaround_value =
QPNP_IADC_RSENSE_DEFAULT_TYPEB_GF;
iadc->default_internal_rsense = true;
} else if (iadc->iadc_comp.id == COMP_ID_SMIC) {
iadc->rsense_workaround_value =
QPNP_IADC_RSENSE_DEFAULT_TYPEB_SMIC;
iadc->default_internal_rsense = true;
}
}
} else if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEC) {
if ((smbb_batt_trm_cnst_rds >
SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_0) &&
(smbb_batt_trm_cnst_rds <=
SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) &&
(trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) {
iadc->rsense_workaround_value =
QPNP_IADC_RSENSE_DEFAULT_VALUE;
iadc->default_internal_rsense = true;
}
}
return 0;
}
static int qpnp_flash_led_module_disable(struct qpnp_flash_led *led,
struct flash_node_data *flash_node)
{
union power_supply_propval psy_prop;
int rc;
u8 val, tmp;
rc = spmi_ext_register_readl(led->spmi_dev->ctrl,
led->spmi_dev->sid,
FLASH_LED_STROBE_CTRL(led->base),
&val, 1);
if (rc) {
dev_err(&led->spmi_dev->dev,
"Unable to read module enable reg\n");
return -EINVAL;
}
tmp = ~flash_node->trigger & val;
if (!tmp) {
if (flash_node->type == TORCH) {
rc = qpnp_led_masked_write(led->spmi_dev,
FLASH_LED_UNLOCK_SECURE(led->base),
FLASH_SECURE_MASK, FLASH_UNLOCK_SECURE);
if (rc) {
dev_err(&led->spmi_dev->dev,
"Secure reg write failed\n");
return -EINVAL;
}
rc = qpnp_led_masked_write(led->spmi_dev,
FLASH_TORCH(led->base),
FLASH_TORCH_MASK, FLASH_LED_TORCH_DISABLE);
if (rc) {
dev_err(&led->spmi_dev->dev,
"Torch reg write failed\n");
return -EINVAL;
}
}
rc = qpnp_led_masked_write(led->spmi_dev,
FLASH_MODULE_ENABLE_CTRL(led->base),
FLASH_MODULE_ENABLE_MASK, FLASH_LED_DISABLE);
if (rc) {
dev_err(&led->spmi_dev->dev, "Module disable failed\n");
return -EINVAL;
}
if (led->battery_psy) {
psy_prop.intval = false;
rc = led->battery_psy->set_property(led->battery_psy,
POWER_SUPPLY_PROP_FLASH_ACTIVE,
&psy_prop);
if (rc) {
dev_err(&led->spmi_dev->dev,
"Failed to setup OTG pulse skip enable\n");
return -EINVAL;
}
}
} else {
rc = qpnp_led_masked_write(led->spmi_dev,
FLASH_MODULE_ENABLE_CTRL(led->base),
flash_node->enable, flash_node->enable);
if (rc) {
dev_err(&led->spmi_dev->dev, "Module disable failed\n");
return -EINVAL;
}
}
return 0;
}
