/* Set up data to get the interface up and running. */
int
sq_init(struct ifnet *ifp)
{
int i;
u_int32_t reg;
struct sq_softc *sc = ifp->if_softc;
/* Cancel any in-progress I/O */
sq_stop(ifp, 0);
sc->sc_nextrx = 0;
sc->sc_nfreetx = SQ_NTXDESC;
sc->sc_nexttx = sc->sc_prevtx = 0;
SQ_TRACE(SQ_RESET, 0, 0, sc->sc_nfreetx);
/* Set into 8003 mode, bank 0 to program ethernet address */
bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCMD, TXCMD_BANK0);
/* Now write the address */
for (i = 0; i < ETHER_ADDR_LEN; i++)
bus_space_write_1(sc->sc_regt, sc->sc_regh, i,
sc->sc_enaddr[i]);
sc->sc_rxcmd = RXCMD_IE_CRC |
RXCMD_IE_DRIB |
RXCMD_IE_SHORT |
RXCMD_IE_END |
RXCMD_IE_GOOD;
/*
* Set the receive filter -- this will add some bits to the
* prototype RXCMD register. Do this before setting the
* transmit config register, since we might need to switch
* banks.
*/
sq_set_filter(sc);
/* Set up Seeq transmit command register */
bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_TXCMD,
TXCMD_IE_UFLOW |
TXCMD_IE_COLL |
TXCMD_IE_16COLL |
TXCMD_IE_GOOD);
/* Now write the receive command register. */
bus_space_write_1(sc->sc_regt, sc->sc_regh, SEEQ_RXCMD, sc->sc_rxcmd);
/* Set up HPC ethernet DMA config */
reg = bus_space_read_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_DMACFG);
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_DMACFG,
reg | ENETR_DMACFG_FIX_RXDC |
ENETR_DMACFG_FIX_INTR |
ENETR_DMACFG_FIX_EOP);
/* Pass the start of the receive ring to the HPC */
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_NDBP,
SQ_CDRXADDR(sc, 0));
/* And turn on the HPC ethernet receive channel */
bus_space_write_4(sc->sc_hpct, sc->sc_hpch, HPC_ENETR_CTL,
ENETR_CTL_ACTIVE);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
return 0;
}
/* Set up data to get the interface up and running. */
int
sq_init(struct ifnet *ifp)
{
int i;
struct sq_softc *sc = ifp->if_softc;
/* Cancel any in-progress I/O */
sq_stop(ifp, 0);
sc->sc_nextrx = 0;
sc->sc_nfreetx = SQ_NTXDESC;
sc->sc_nexttx = sc->sc_prevtx = 0;
SQ_TRACE(SQ_RESET, sc, 0, 0);
/* Set into 8003 mode, bank 0 to program ethernet address */
sq_seeq_write(sc, SEEQ_TXCMD, TXCMD_BANK0);
/* Now write the address */
for (i = 0; i < ETHER_ADDR_LEN; i++)
sq_seeq_write(sc, i, sc->sc_enaddr[i]);
sc->sc_rxcmd =
RXCMD_IE_CRC |
RXCMD_IE_DRIB |
RXCMD_IE_SHORT |
RXCMD_IE_END |
RXCMD_IE_GOOD;
/*
* Set the receive filter -- this will add some bits to the
* prototype RXCMD register. Do this before setting the
* transmit config register, since we might need to switch
* banks.
*/
sq_set_filter(sc);
/* Set up Seeq transmit command register */
sq_seeq_write(sc, SEEQ_TXCMD,
TXCMD_IE_UFLOW |
TXCMD_IE_COLL |
TXCMD_IE_16COLL |
TXCMD_IE_GOOD);
/* Now write the receive command register. */
sq_seeq_write(sc, SEEQ_RXCMD, sc->sc_rxcmd);
/*
* Set up HPC ethernet PIO and DMA configurations.
*
* The PROM appears to do most of this for the onboard HPC3, but
* not for the Challenge S's IOPLUS chip. We copy how the onboard
* chip is configured and assume that it's correct for both.
*/
if (sc->hpc_regs->revision == 3) {
uint32_t dmareg, pioreg;
pioreg =
HPC3_ENETR_PIOCFG_P1(1) |
HPC3_ENETR_PIOCFG_P2(6) |
HPC3_ENETR_PIOCFG_P3(1);
dmareg =
HPC3_ENETR_DMACFG_D1(6) |
HPC3_ENETR_DMACFG_D2(2) |
HPC3_ENETR_DMACFG_D3(0) |
HPC3_ENETR_DMACFG_FIX_RXDC |
HPC3_ENETR_DMACFG_FIX_INTR |
HPC3_ENETR_DMACFG_FIX_EOP |
HPC3_ENETR_DMACFG_TIMEOUT;
sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg);
sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg);
}
/* Pass the start of the receive ring to the HPC */
sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0));
/* And turn on the HPC ethernet receive channel */
sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
sc->hpc_regs->enetr_ctl_active);
/*
* Turn off delayed receive interrupts on HPC1.
* (see Hollywood HPC Specification 2.1.4.3)
*/
if (sc->hpc_regs->revision != 3)
sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
return 0;
}
