void spm_dpidle_before_wfi(void)
{
    if (TRUE == mt_dpidle_chk_golden)
    {
    //FIXME:
#if 0
        mt_power_gs_dump_dpidle();
#endif
    }
    bus_dcm_enable();
    clkmgr_faudintbus_pll2sq();
    //clkmux_sel(MT_MUX_AUDINTBUS, 0, "Deepidle"); //select 26M


#ifdef CONFIG_SMP
    dpidle_timer_left2 = localtimer_get_counter();

    if( (int)dpidle_timer_left2 <=0 )
        gpt_set_cmp(idle_gpt, 1);//Trigger GPT4 Timerout imediately
    else
        gpt_set_cmp(idle_gpt, dpidle_timer_left2);

    start_gpt(idle_gpt);
#else
    gpt_get_cnt(idle_gpt, &dpidle_timer_left2);
#endif
}
void soidle_before_wfi(void)
{
#ifdef CONFIG_SMP
    int err = 0;

    soidle_timer_left2 = localtimer_get_counter();

    free_gpt(GPT4);
    err = request_gpt(GPT4, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                      0, NULL, GPT_NOAUTOEN);
    if (err) {
        idle_info("[%s]fail to request GPT4\n", __func__);
    }

    soidle_timer_left2 = localtimer_get_counter();

    if( soidle_timer_left2 <=0 )
        gpt_set_cmp(GPT4, 1);//Trigger GPT4 Timerout imediately
    else
        gpt_set_cmp(GPT4, soidle_timer_left2);

    start_gpt(GPT4);
#else
    gpt_get_cnt(GPT1, &soidle_timer_left2);
#endif

}
void spm_dpidle_before_wfi(void)
{

    int err = 0;


    g_clk_aud_intbus_sel = clkmux_get(MT_CLKMUX_AUD_INTBUS_SEL,"Deep_Idle");
    clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL, MT_CG_SYS_26M,"Deep_Idle");

    enable_clock(MT_CG_PMIC_SW_CG_AP, "DEEP_IDLE");//PMIC CG bit for AP. SPM need PMIC wrapper clock to change Vcore voltage
#ifdef CONFIG_SMP

    free_gpt(GPT4);
    err = request_gpt(GPT4, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                      0, NULL, GPT_NOAUTOEN);

    if (err) {
        idle_info("[%s]fail to request GPT4\n", __func__);
    }

    dpidle_timer_left2 = localtimer_get_counter();

    if( dpidle_timer_left2 <=0 )
        gpt_set_cmp(GPT4, 1);//Trigger GPT4 Timerout imediately
    else
        gpt_set_cmp(GPT4, dpidle_timer_left2);

    start_gpt(GPT4);
#else
    gpt_get_cnt(GPT1, &dpidle_timer_left2);
#endif

}
Exemple #4
0
void soidle_before_wfi(int cpu)
{
    int err = 0;
    unsigned int id = soidle_gpt_percpu[cpu];
    
        free_gpt(id);
        err = request_gpt(id, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1, 
                    0, NULL, GPT_NOAUTOEN);
        if (err) {
            idle_info("[%s]fail to request GPT4\n", __func__);
        }
    
        soidle_timer_left2[cpu] = localtimer_get_counter(); 


        if( (int)soidle_timer_left2[cpu] <=0 )
        {
            gpt_set_cmp(id, 1);//Trigger GPT4 Timerout imediately
        }
        else    
            gpt_set_cmp(id, soidle_timer_left2[cpu]);
        
        start_gpt(id);

}
void spm_mcdi_before_wfi(int cpu)
{
    unsigned int id = mcidle_gpt_percpu[cpu];
    if (cpu != 0) {
        mcidle_timer_left2[cpu] = localtimer_get_counter(); 
#ifdef SPM_SUSPEND_GPT_EN
        err = request_gpt(id, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1, 
                    0, NULL, GPT_NOAUTOEN);
        if (err) {
            idle_info("[%s]fail to request GPT4\n", __func__);
        }
#endif        
        gpt_set_cmp(id, mcidle_timer_left2[cpu]);
        start_gpt(id);
    }
}
void soidle_before_wfi(int cpu)
{
#ifdef CONFIG_SMP
    soidle_timer_left2 = localtimer_get_counter();

    if( (int)soidle_timer_left2 <=0 )
    {
        gpt_set_cmp(idle_gpt, 1);//Trigger idle_gpt Timerout imediately
    }
    else
        gpt_set_cmp(idle_gpt, soidle_timer_left2);

    start_gpt(idle_gpt);
#else
    gpt_get_cnt(GPT1, &soidle_timer_left2);
#endif

}
Exemple #7
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void spm_dpidle_before_wfi(void)
{
    if (TRUE == mt_dpidle_chk_golden)
    {
        mt_power_gs_dump_dpidle();
    }

    bus_dcm_enable();

    faudintbus_pll2sq();

#if 0
        dpidle_timer_left = localtimer_get_counter();
        gpt_set_cmp(GPT4, dpidle_timer_left);
#else
        dpidle_timer_left2 = localtimer_get_counter();
        gpt_set_cmp(GPT4, dpidle_timer_left2);
#endif
        start_gpt(GPT4);

}
void mcidle_before_wfi(int cpu)
{
#ifdef CONFIG_SMP
    int err = 0;

    unsigned int id = mcidle_gpt_percpu[cpu];

    mcidle_timer_left2[cpu] = localtimer_get_counter();

    free_gpt(id);
    err = request_gpt(id, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                      0, NULL, GPT_NOAUTOEN);
    if (err) {
        idle_info("[%s]fail to request GPT4\n", __func__);
    }

    mcidle_timer_left2[cpu] = localtimer_get_counter();


    if(cpu!=0)//core1~n, avoid gpt clear by core0
    {
        if( mcidle_timer_left2[cpu] <=2600 ) //200us(todo)
        {
            if(mcidle_timer_left2[cpu]<=0)
                gpt_set_cmp(id, 1);//Trigger GPT4 Timerout imediately
            else
                gpt_set_cmp(id, mcidle_timer_left2[cpu]);

            spm_write(SPM_SLEEP_CPU_WAKEUP_EVENT,spm_read(SPM_SLEEP_CPU_WAKEUP_EVENT)|0x1);//spm wake up directly

        }
        else
            gpt_set_cmp(id, mcidle_timer_left2[cpu]);

        start_gpt(id);
    }
#else
    gpt_get_cnt(GPT1, &mcidle_timer_left2);
#endif
}
void soidle_before_wfi(int cpu)
{
#ifdef CONFIG_SMP
	#if !defined(SODI_APxGPT_TimerCount) || (SODI_APxGPT_TimerCount == 0)
	soidle_timer_left2 = localtimer_get_counter();
	#else
	soidle_timer_left2 = 13000000*SODI_APxGPT_TimerCount;
	#endif

    if( (int)soidle_timer_left2 <=0 )
    {
        gpt_set_cmp(idle_gpt, 1);//Trigger idle_gpt Timerout imediately
    }
    else
    {
        gpt_set_cmp(idle_gpt, soidle_timer_left2);
    }

    start_gpt(idle_gpt);
#else
    gpt_get_cnt(GPT1, &soidle_timer_left2);
#endif

}
Exemple #10
0
int spm_wfi_for_mcdi_test(void *mcdi_data)
{   
    volatile u32 do_not_change_it;
    volatile u32 lo, hi, core_id;
    unsigned long flags;

    preempt_disable();
    do_not_change_it = 1;
    MCDI_Test_Mode = 1;

    while(do_not_change_it)     
    {
        /* Mask ARM i bit */
        local_irq_save(flags);
    
        core_id = (u32)smp_processor_id();

        // set local timer & GPT =========================================
        switch (core_id)
        {
            case 0 : 


                #if 0
                /*trigger pcm timer*/
                spm_write(SPM_POWER_ON_VAL1,(spm_read(SPM_POWER_ON_VAL1)&0xFFFFFFCF)|0x220);
                spm_write(SPM_PCM_PWR_IO_EN,0x00800000);
                spm_write(SPM_PCM_PWR_IO_EN,0x00000000);
                #else
                read_cntp_cval(lo, hi);
                lo+=26000; // 100 ms, 13MHz
                //lo+=5070000; // 390 ms, 13MHz
                write_cntp_cval(lo, hi);
                write_cntp_ctl(0x1);  // CNTP_CTL_ENABLE      
                //printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
                #endif


                
            break;       
            
            case 1 : 
                #if 0
                //gpt_set_cmp(GPT4, 2470000); // 190ms, 13MHz
                //printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
                gpt_set_cmp(GPT4, 130000); // 10ms, 13MHz
                start_gpt(GPT4);   
                #endif
                read_cntp_cval(lo, hi);
                lo+=26000; // 100 ms, 13MHz
                //lo+=5070000; // 390 ms, 13MHz
                write_cntp_cval(lo, hi);
                write_cntp_ctl(0x1);  // CNTP_CTL_ENABLE   

                spm_mcdi_before_wfi(core_id);          
                

                
            break;          
    
            
            default : break;
        }

        spm_mcdi_wfi();
        
        if(core_id==1)
            spm_mcdi_after_wfi(core_id);
        
        /* Un-Mask ARM i bit */
        local_irq_restore(flags);
    }
    
    preempt_enable();
    return 0;

}