static void board_bt_deinit_pins(void)
{
stm32_gpiowrite(GPIO_BT_RESET_N, true);
stm32_gpiowrite(GPIO_BT_RESET_N, false);
stm32_gpiowrite(GPIO_REGULATOR_BLUETOOTH, false);
if (board_get_hw_ver() < BOARD_HWVER_B2_0)
{
stm32_unconfiggpio(GPIO_BT_RESERVED1);
stm32_unconfiggpio(GPIO_BT_RESERVED2);
}
stm32_gpiowrite(GPIO_BT_RESERVED3, false);/*Backdoor enabled -> !supplyvolt */
}
/**
* @brief Deinitialize dedicated current measurement HW
* (GPIO, ADC) of a given spring.
* warning 'spring' index starts at 1, not 0.
* @return 0 on success, standard error otherwise.
* @param[in] spring: selected spring ([1..SPRING_COUNT])
*/
int spwrm_deinit(uint8_t spring)
{
int ret;
uint8_t adc, chan;
uint32_t spin;
CHECK_SPRING(spring);
dbg_verbose("%s(): De-initializing %s...\n", __func__,
spwrm_get_name(spring));
adc = spwrm_get_adc_device(spring);
chan = spwrm_get_adc_channel(spring);
spin = spwrm_get_sign_pin(spring);
/* Unconfigure GPIO ADC channel pin */
stm32_unconfiggpio(spin);
/* Shutdown ADC */
ret = adc_deinit(adc, chan);
if (ret) {
dbg_error("%s(): %s de-initialization failed!!! (%d)\n", __func__,
spwrm_get_name(spring), ret);
} else {
dbg_verbose("%s(): %s de-initialization done.\n", __func__,
spwrm_get_name(spring));
}
return ret;
}
/**
* Gain is set using the shared multiplexed bus with the SDIO card.
* The following rules apply for the SDcard:
*
* - CMD serial line always starts with 0 (start-bit) and ends with 1 (stop-bit)
* The total length is always 48 bits protected by CRCs. When changing the
* gain, CMD must be seen as 1 on CK changes.
*
* - An alternative mechanism would be to use suspend/resume commands
*
* - If SDcard internal shift-register is 8-bit oriented there might be a need
* to shift 7 dummy bits to properly detect invalid start of packet
* (with start bit set as 1) to invalidate bus transitions (in case CK
* is changing).
*
* SDIO returns the bus in HiZ states, where CLK = 0, D = CMD = external pull-up
*/
int sif_anin_setgain(int gain)
{
/* Shutdown the PGA and exit if gain is invalid */
stm32_gpiowrite(GPIO_PGIA_AEN, FALSE);
if (gain < 0 || gain > 7)
return -1;
sdio_gpio_request();
/* If we have to set CLK = 1, made that first as D, CMD are 1 by pull-ups */
if (gain & 2)
stm32_configgpio(GPIO_PGIA_A1_H);
else stm32_configgpio(GPIO_PGIA_A1_L);
/* Set the D and CMD bits */
if (gain & 1)
stm32_configgpio(GPIO_PGIA_A0_H);
else stm32_configgpio(GPIO_PGIA_A0_L);
if (gain & 4)
stm32_configgpio(GPIO_PGIA_A2_H);
else stm32_configgpio(GPIO_PGIA_A2_L);
/* Sample GAIN on rising edge */
stm32_gpiowrite(GPIO_PGIA_AEN, TRUE);
/* Release D and CMD pins to 1; however shorten rising edge actively */
stm32_gpiowrite(GPIO_PGIA_A0_H, TRUE);
stm32_gpiowrite(GPIO_PGIA_A2_H, TRUE);
stm32_unconfiggpio(GPIO_PGIA_A0_H);
stm32_unconfiggpio(GPIO_PGIA_A2_H);
/* Release CLK by going down */
stm32_unconfiggpio(GPIO_PGIA_A1_L);
sdio_gpio_release();
return gain;
}
PX4IO_serial::~PX4IO_serial()
{
if (_tx_dma != nullptr) {
stm32_dmastop(_tx_dma);
stm32_dmafree(_tx_dma);
}
if (_rx_dma != nullptr) {
stm32_dmastop(_rx_dma);
stm32_dmafree(_rx_dma);
}
/* reset the UART */
rCR1 = 0;
rCR2 = 0;
rCR3 = 0;
/* detach our interrupt handler */
up_disable_irq(PX4IO_SERIAL_VECTOR);
irq_detach(PX4IO_SERIAL_VECTOR);
/* restore the GPIOs */
stm32_unconfiggpio(PX4IO_SERIAL_TX_GPIO);
stm32_unconfiggpio(PX4IO_SERIAL_RX_GPIO);
/* and kill our semaphores */
sem_destroy(&_completion_semaphore);
sem_destroy(&_bus_semaphore);
perf_free(_pc_txns);
perf_free(_pc_dmasetup);
perf_free(_pc_retries);
perf_free(_pc_timeouts);
perf_free(_pc_crcerrs);
perf_free(_pc_dmaerrs);
perf_free(_pc_protoerrs);
perf_free(_pc_uerrs);
perf_free(_pc_idle);
perf_free(_pc_badidle);
if (g_interface == this) {
g_interface = nullptr;
}
}
static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
{
/** \todo Added support for input capture and bipolar dual outputs for TIM8 */
if (mode & STM32_TIM_CH_MODE_MASK) {
stm32_configgpio(cfg);
}
else {
stm32_unconfiggpio(cfg);
}
}
// Configure pin as input floating
static void stm32_gpio_deactivate(void *driver_data, uint8_t pin)
{
uint32_t cfgset;
int ret;
lldbg("%s: pin=%hhu\n", __func__, pin);
ret = map_pin_nr_to_cfgset(pin, &cfgset);
if (ret) {
lldbg("%s: Invalid pin %hhu\n", pin);
return;
}
stm32_unconfiggpio(cfgset);
}
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev)
{
const struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint32_t gpio;
DEBUGASSERT(dev != NULL);
/* Disable timer while is not configured */
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
gpio = stm32_cap_gpio(priv, STM32_CAP_CHANNEL_COUNTER);
if (gpio)
{
stm32_unconfiggpio(gpio);
}
stm32_cap_set_rcc(priv, false);
return OK;
}
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
stm32_cap_ch_cfg_t cfg)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint32_t gpio = 0;
uint16_t mask;
uint16_t regval;
uint16_t ccer_en_bit;
DEBUGASSERT(dev != NULL);
gpio = stm32_cap_gpio(priv, channel);
if (gpio == 0)
{
return ERROR;
}
if ((cfg & STM32_CAP_MAPPED_MASK) == 0)
{
return ERROR; /* MAPPED not selected */
}
/* Change to zero base index */
channel--;
/* Set ccer :
*
* GTIM_CCER_CCxE Is written latter to allow writing CCxS bits.
*
*/
switch (cfg & STM32_CAP_EDGE_MASK)
{
case STM32_CAP_EDGE_DISABLED:
regval = 0;
ccer_en_bit = 0;
break;
case STM32_CAP_EDGE_RISING:
ccer_en_bit = GTIM_CCER_CC1E;
regval = 0;
break;
case STM32_CAP_EDGE_FALLING:
ccer_en_bit = GTIM_CCER_CC1E;
regval = GTIM_CCER_CC1P;
break;
case STM32_CAP_EDGE_BOTH:
ccer_en_bit = GTIM_CCER_CC1E;
regval = GTIM_CCER_CC1P | GTIM_CCER_CC1NP;
break;
default:
return ERROR;
}
/* Shift all CCER bits to corresponding channel */
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
mask <<= (channel << 2);
regval <<= (channel << 2);
ccer_en_bit <<= (channel << 2);
stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval);
/* Set ccmr */
regval = cfg;
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK);
regval &= mask;
if (channel & 1)
{
regval <<= 8;
mask <<= 8;
}
if (channel < 2)
{
stm32_modifyreg16(priv, STM32_GTIM_CCMR1_OFFSET, mask, regval);
}
else
{
stm32_modifyreg16(priv, STM32_GTIM_CCMR2_OFFSET, mask, regval);
}
/* Set GPIO */
if ((cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED)
{
stm32_unconfiggpio(gpio);
}
else
{
stm32_configgpio(gpio);
}
/* Enable this channel timer */
stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, 0, ccer_en_bit);
return OK;
}
