void gendsubu(void)
{
#ifdef INTERPRET_DSUBU
gencallinterp((unsigned int)cached_interpreter_table.DSUBU, 0);
#else
int rs1 = allocate_64_register1((unsigned int *)dst->f.r.rs);
int rs2 = allocate_64_register2((unsigned int *)dst->f.r.rs);
int rt1 = allocate_64_register1((unsigned int *)dst->f.r.rt);
int rt2 = allocate_64_register2((unsigned int *)dst->f.r.rt);
int rd1 = allocate_64_register1_w((unsigned int *)dst->f.r.rd);
int rd2 = allocate_64_register2_w((unsigned int *)dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(rd1, rs1);
mov_reg32_reg32(rd2, rs2);
sub_reg32_reg32(rd1, rt1);
sbb_reg32_reg32(rd2, rt2);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs1);
sub_reg32_reg32(temp, rt1);
mov_reg32_reg32(rd1, temp);
mov_reg32_reg32(temp, rs2);
sbb_reg32_reg32(temp, rt2);
mov_reg32_reg32(rd2, temp);
}
#endif
}
void gendsub()
{
#ifdef INTERPRET_DSUB
gencallinterp((unsigned long)DSUB, 0);
#else
int rs1 = allocate_64_register1((unsigned long *)dst->f.r.rs);
int rs2 = allocate_64_register2((unsigned long *)dst->f.r.rs);
int rt1 = allocate_64_register1((unsigned long *)dst->f.r.rt);
int rt2 = allocate_64_register2((unsigned long *)dst->f.r.rt);
int rd1 = allocate_64_register1_w((unsigned long *)dst->f.r.rd);
int rd2 = allocate_64_register2_w((unsigned long *)dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(rd1, rs1);
mov_reg32_reg32(rd2, rs2);
sub_reg32_reg32(rd1, rt1);
sbb_reg32_reg32(rd2, rt2);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs1);
sub_reg32_reg32(temp, rt1);
mov_reg32_reg32(rd1, temp);
mov_reg32_reg32(temp, rs2);
sbb_reg32_reg32(temp, rt2);
mov_reg32_reg32(rd2, temp);
}
#endif
}
void gensubu(void)
{
#if defined(COUNT_INSTR)
inc_m32abs(&instr_count[82]);
#endif
#ifdef INTERPRET_SUBU
gencallinterp((unsigned long long)SUBU, 0);
#else
int rs = allocate_register_32((unsigned int *)dst->f.r.rs);
int rt = allocate_register_32((unsigned int *)dst->f.r.rt);
int rd = allocate_register_32_w((unsigned int *)dst->f.r.rd);
if (rs == rd)
sub_reg32_reg32(rd, rt);
else if (rt == rd)
{
neg_reg32(rd);
add_reg32_reg32(rd, rs);
}
else
{
mov_reg32_reg32(rd, rs);
sub_reg32_reg32(rd, rt);
}
#endif
}
void gendsub(usf_state_t * state)
{
#ifdef INTERPRET_DSUB
gencallinterp(state, (unsigned int)state->current_instruction_table.DSUB, 0);
#else
int rs1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rs);
int rs2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rs);
int rt1 = allocate_64_register1(state, (unsigned int *)state->dst->f.r.rt);
int rt2 = allocate_64_register2(state, (unsigned int *)state->dst->f.r.rt);
int rd1 = allocate_64_register1_w(state, (unsigned int *)state->dst->f.r.rd);
int rd2 = allocate_64_register2_w(state, (unsigned int *)state->dst->f.r.rd);
if (rt1 != rd1 && rs1 != rd1)
{
mov_reg32_reg32(state, rd1, rs1);
mov_reg32_reg32(state, rd2, rs2);
sub_reg32_reg32(state, rd1, rt1);
sbb_reg32_reg32(state, rd2, rt2);
}
else
{
int temp = lru_register(state);
free_register(state, temp);
mov_reg32_reg32(state, temp, rs1);
sub_reg32_reg32(state, temp, rt1);
mov_reg32_reg32(state, rd1, temp);
mov_reg32_reg32(state, temp, rs2);
sbb_reg32_reg32(state, temp, rt2);
mov_reg32_reg32(state, rd2, temp);
}
#endif
}
void gensubu()
{
#ifdef INTERPRET_SUBU
gencallinterp((unsigned long)SUBU, 0);
#else
int rs = allocate_register((unsigned long *)dst->f.r.rs);
int rt = allocate_register((unsigned long *)dst->f.r.rt);
int rd = allocate_register_w((unsigned long *)dst->f.r.rd);
if (rt != rd && rs != rd)
{
mov_reg32_reg32(rd, rs);
sub_reg32_reg32(rd, rt);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs);
sub_reg32_reg32(temp, rt);
mov_reg32_reg32(rd, temp);
}
#endif
}
void gensub(void)
{
#ifdef INTERPRET_SUB
gencallinterp((unsigned int)cached_interpreter_table.SUB, 0);
#else
int rs = allocate_register((unsigned int *)dst->f.r.rs);
int rt = allocate_register((unsigned int *)dst->f.r.rt);
int rd = allocate_register_w((unsigned int *)dst->f.r.rd);
if (rt != rd && rs != rd)
{
mov_reg32_reg32(rd, rs);
sub_reg32_reg32(rd, rt);
}
else
{
int temp = lru_register();
free_register(temp);
mov_reg32_reg32(temp, rs);
sub_reg32_reg32(temp, rt);
mov_reg32_reg32(rd, temp);
}
#endif
}
void gensubu(usf_state_t * state)
{
#ifdef INTERPRET_SUBU
gencallinterp(state, (unsigned int)state->current_instruction_table.SUBU, 0);
#else
int rs = allocate_register(state, (unsigned int *)state->dst->f.r.rs);
int rt = allocate_register(state, (unsigned int *)state->dst->f.r.rt);
int rd = allocate_register_w(state, (unsigned int *)state->dst->f.r.rd);
if (rt != rd && rs != rd)
{
mov_reg32_reg32(state, rd, rs);
sub_reg32_reg32(state, rd, rt);
}
else
{
int temp = lru_register(state);
free_register(state, temp);
mov_reg32_reg32(state, temp, rs);
sub_reg32_reg32(state, temp, rt);
mov_reg32_reg32(state, rd, temp);
}
#endif
}
