static void sun4c_intctl_reset(void *opaque) { Sun4c_INTCTLState *s = opaque; s->reg = 1; s->pending = 0; sun4c_check_interrupts(s); }
static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { Sun4c_INTCTLState *s = opaque; DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val); val &= 0xbf; s->reg = val; sun4c_check_interrupts(s); }
static void sun4c_intctl_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { Sun4c_INTCTLState *s = opaque; DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val); val &= 0xbf; s->reg = val; sun4c_check_interrupts(s); }
static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id) { Sun4c_INTCTLState *s = opaque; if (version_id != 1) return -EINVAL; qemu_get_8s(f, &s->reg); qemu_get_8s(f, &s->pending); sun4c_check_interrupts(s); return 0; }
/* * "irq" here is the bit number in the system interrupt register */ static void sun4c_set_irq(void *opaque, int irq, int level) { Sun4c_INTCTLState *s = opaque; uint32_t mask = 1 << irq; uint32_t pil = intbit_to_level[irq]; DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil, level); if (pil > 0) { if (level) { #ifdef DEBUG_IRQ_COUNT s->irq_count++; #endif s->pending |= mask; } else { s->pending &= ~mask; } sun4c_check_interrupts(s); } }