/*
* Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
*/
static void spi0_pinmux_setup(unsigned int pin_function)
{
unsigned int pin;
for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
sunxi_gpio_set_cfgpin(pin, pin_function);
if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
else
sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
}
static void sunxi_lcdc_backlight_enable(void)
{
int pin;
/*
* We want to have scanned out at least one frame before enabling the
* backlight to avoid the screen flashing to white when we enable it.
*/
mdelay(40);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
if (pin >= 0)
gpio_direction_output(pin, 1);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
#ifdef SUNXI_PWM_PIN0
if (pin == SUNXI_PWM_PIN0) {
writel(SUNXI_PWM_CTRL_POLARITY0(PWM_ON) |
SUNXI_PWM_CTRL_ENABLE0 |
SUNXI_PWM_CTRL_PRESCALE0(0xf), SUNXI_PWM_CTRL_REG);
writel(SUNXI_PWM_PERIOD_80PCT, SUNXI_PWM_CH0_PERIOD);
sunxi_gpio_set_cfgpin(pin, SUNXI_PWM_MUX);
return;
}
#endif
if (pin >= 0)
gpio_direction_output(pin, PWM_ON);
}
void i2c_init(int speed, int slaveaddr)
{
int timeout = 0x2ff;
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2);
clock_twi_onoff(0, 1);
/* Enable the i2c bus */
writel(TWI_CTL_BUSEN, &i2c_base->ctl);
/* 400KHz operation M=2, N=1, 24MHz APB clock */
writel(TWI_CLK_DIV(2, 1), &i2c_base->clkr);
writel(TWI_SRST_SRST, &i2c_base->reset);
while ((readl(&i2c_base->reset) & TWI_SRST_SRST) && timeout--);
}
int init_lcd_pin_direction() {
// GPIO2 LCD
// 1 +5V -> 2 VDD
// 2 Ground -> 1 GND
//
// 3 +3.3V EMPTY
// 4 Ground EMPTY
//
//
// 5 PB0 (TWI0-SCK) -> 4 RS
// 6 PG11 (USBH_EN) -> 5 R/W
// 7 PB1 (TWI0-SDA) -> 6 E
//
// 8 PG10 (VGA_DIS) -> 7 DB0
// 10 PG9 (LED1) -> 8 DB1
// 11 PB3 -> 9 DB2
// 12 PE11 -> 10 DB3
// 13 PB4 -> 11 DB4
// 14 PE10 -> 12 DB5
// 16 PE9 -> 13 DB6
// 18 PE8 -> 14 DB7
// 9 PB2 (PWM0) ERROR
// 15 PB10 ERROR
// 17 PB15 (TWI1-SCK) ERROR
int ret;
//init gpio
ret = sunxi_gpio_init();
if(ret) {
printf("sunxi_gpio_init ERROR\n");
return -1;
}
/* //RS, R/W, E
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPIO_OUTPUT);
//DB0 - DB7
sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPG(9), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(3), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPE(11), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(4), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPE(10), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPE(9), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPE(8), SUNXI_GPIO_OUTPUT);
*/
sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUNXI_GPIO_OUTPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPG(9), SUNXI_GPIO_OUTPUT);
return 0;
}
int gpio_direction_input(unsigned gpio)
{
#ifdef AXP_GPIO
if (gpio >= SUNXI_GPIO_AXP0_START)
return axp_gpio_direction_input(gpio - SUNXI_GPIO_AXP0_START);
#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
return 0;
}
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
#elif defined CONFIG_MACH_SUN9I
sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
#else
#error unsupported MACH_SUNXI
#endif
}
int gpio_direction_output(unsigned gpio, int value)
{
#ifdef AXP_GPIO
if (gpio >= SUNXI_GPIO_AXP0_START)
return axp_gpio_direction_output(gpio - SUNXI_GPIO_AXP0_START,
value);
#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
return sunxi_gpio_output(gpio, value);
}
/**
* Set configuration. See A20 datasheet for correct values.
*
* @param self
* @param args GPIO number and configuration value
* @return none
*/
static PyObject* py_setcfg(PyObject* self, PyObject* args) {
int gpio;
int cfg;
/* Parse arguments. Require two integers for GPIO number and configuration */
if (!PyArg_ParseTuple(args, "ii", &gpio, &cfg))
return NULL;
/* Set configuration and check return status */
if (sunxi_gpio_set_cfgpin(gpio, cfg) < 0) {
return PyErr_SetFromErrno(PyExc_IOError);
}
Py_RETURN_NONE;
}
int sunxi_gmac_initialize(bd_t *bis)
{
int pin;
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
#else
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII);
#endif
/*
* In order for the gmac nic to work reliable on the Bananapi, we
* need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
* of the GMAC clk register to 3.
*/
#ifdef CONFIG_TARGET_BANANAPI
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
#else
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
}
int sunxi_gmac_initialize(bd_t *bis)
{
int pin;
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
/* Set MII clock */
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
#else
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII);
#endif
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
sunxi_gpio_set_cfgpin(pin, 5);
sunxi_gpio_set_drv(pin, 3);
}
#ifdef CONFIG_RGMII
designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
#else
designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
#endif
return 0;
}
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
int *clk_div, int *clk_double,
bool use_portd_hvsync)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, total, val, yres;
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
((mode->vmode == FB_VMODE_INTERLACED) ?
SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
yres = mode->yres;
if (mode->vmode == FB_VMODE_INTERLACED)
yres /= 2;
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
if (mode->vmode == FB_VMODE_NONINTERLACED)
total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon1_timing_sync);
if (use_portd_hvsync) {
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
val = 0;
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
writel(val, &lcdc->tcon1_io_polarity);
clrbits_le32(&lcdc->tcon1_io_tristate,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
#ifdef CONFIG_MACH_SUN5I
if (sunxi_is_composite())
clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
SUNXI_LCDC_MUX_CTRL_SRC0(1));
#endif
sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
}
/*
* pinMode:
* Sets the mode of a pin to be INPUT, OUTPUT
*********************************************************************************
*/
void pinMode(int pin, int mode)
{
sunxi_gpio_set_cfgpin(pinWiringOli(pin), mode);
}
void main (int argc, char **argv)
{
int pulseDelay=1000;
if (argc >= 2) {
pulseDelay = atoi(argv[1]);
}
printf("%d", pulseDelay);
fflush(stdout);
//return;
// We'll operate on the currently running thread.
pthread_t this_thread = pthread_self();
// struct sched_param is used to store the scheduling priority
struct sched_param params;
// We'll set the priority to the maximum.
params.sched_priority = sched_get_priority_max(SCHED_FIFO);
// Attempt to set thread real-time priority to the SCHED_FIFO policy
int ret = pthread_setschedparam(this_thread, SCHED_FIFO, ¶ms);
if (ret != 0) {
// Print the error
//std::cout << "Unsuccessful in setting thread realtime prio" << std::endl;
return;
}
sunxi_gpio_init();
sunxi_gpio_set_cfgpin(SERVO_PIN, PIN_OUTPUT);
int callpointer = sunxi_gpio_getCallPointer(SERVO_PIN);
int pindef = sunxi_gpio_getPindef(SERVO_PIN);
const long frameLenght = 1000 * NANO_SECOND_MULTIPLIER;
struct timespec onInterval = {0};
struct timespec offInterval = {0};
onInterval.tv_nsec = pulseDelay * 1000;
//sunxi_gpio_output(SERVO_PIN, 1);
/*
while(1){
*/
int i;
struct timeval tStart, tStop, tLen;
//for(i = 0;i<50;i++){
while(1){
gettimeofday (&tStart, NULL) ;
sunxi_gpio_setFastOn(callpointer,pindef);
// Berechnen wie lang man den Pulse einschalten sollte:
gettimeofday (&tStop, NULL);
timersub(&tStop,&tStart,&tLen);
onInterval.tv_nsec = pulseDelay * 1000;;
onInterval.tv_nsec -= tLen.tv_usec * 1000 ;
nanosleep(&onInterval, NULL);
sunxi_gpio_setFastOff(callpointer,pindef);
//sunxi_gpio_output(SERVO_PIN, 0);
// Berechnen wie lang noch schlafen:
gettimeofday (&tStop, NULL);
// TimesStop - TimeStart = TLen
timersub(&tStop,&tStart,&tLen);
offInterval.tv_nsec = frameLenght;
offInterval.tv_nsec -= tLen.tv_usec * 1000 ;
nanosleep(&offInterval, NULL);
//return;
//
//nanosleep(&offInterval, NULL);
}
}
int sunxi_gmac_initialize(bd_t *bis)
{
int pin;
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
#else
setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
#endif
/* Set MII clock */
#ifdef CONFIG_RGMII
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
CCM_GMAC_CTRL_GPIT_RGMII);
setbits_le32(&ccm->gmac_clk_cfg,
CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
#else
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII);
#endif
#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_RGMII
/* Configure sun6i RGMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_GMII
/* Configure sun6i GMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 2);
}
#else
/* Configure sun6i MII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
#ifdef CONFIG_DM_ETH
return 0;
#else
# ifdef CONFIG_RGMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
# elif defined CONFIG_GMII
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
# else
return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
# endif
#endif
}
static int sun4i_spi_parse_pins(struct udevice *dev)
{
const void *fdt = gd->fdt_blob;
const char *pin_name;
const fdt32_t *list;
u32 phandle;
int drive, pull = 0, pin, i;
int offset;
int size;
list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
if (!list) {
printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
return -EINVAL;
}
while (size) {
phandle = fdt32_to_cpu(*list++);
size -= sizeof(*list);
offset = fdt_node_offset_by_phandle(fdt, phandle);
if (offset < 0)
return offset;
drive = fdt_getprop_u32_default_node(fdt, offset, 0,
"drive-strength", 0);
if (drive) {
if (drive <= 10)
drive = 0;
else if (drive <= 20)
drive = 1;
else if (drive <= 30)
drive = 2;
else
drive = 3;
} else {
drive = fdt_getprop_u32_default_node(fdt, offset, 0,
"allwinner,drive",
0);
drive = min(drive, 3);
}
if (fdt_get_property(fdt, offset, "bias-disable", NULL))
pull = 0;
else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
pull = 1;
else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
pull = 2;
else
pull = fdt_getprop_u32_default_node(fdt, offset, 0,
"allwinner,pull",
0);
pull = min(pull, 2);
for (i = 0; ; i++) {
pin_name = fdt_stringlist_get(fdt, offset,
"pins", i, NULL);
if (!pin_name) {
pin_name = fdt_stringlist_get(fdt, offset,
"allwinner,pins",
i, NULL);
if (!pin_name)
break;
}
pin = name_to_gpio(pin_name);
if (pin < 0)
break;
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
sunxi_gpio_set_drv(pin, drive);
sunxi_gpio_set_pull(pin, pull);
}
}
return 0;
}
int gpio_direction_input(unsigned gpio)
{
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
return sunxi_gpio_input(gpio);
}
int gpio_direction_output(unsigned gpio, int value)
{
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
return sunxi_gpio_output(gpio, value);
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int clk_div, clk_double, pin;
struct display_timing timing;
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
#else
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#endif
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
sunxi_gpio_set_drv(pin, 3);
#endif
}
lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
sunxi_is_composite());
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
}
#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
int *clk_div, int *clk_double,
bool use_portd_hvsync)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct display_timing timing;
sunxi_ctfb_mode_to_display_timing(mode, &timing);
lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
sunxi_is_composite());
if (use_portd_hvsync) {
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
}
lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
sunxi_is_composite());
}
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
#ifdef CONFIG_VIDEO_HDMI
static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
u8 checksum = 0;
u8 avi_info_frame[17] = {
0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00
};
u8 vendor_info_frame[19] = {
0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00
};
int i;
if (mode->pixclock_khz <= 27000)
avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
else
avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
if (mode->xres * 100 / mode->yres < 156)
avi_info_frame[5] |= 0x18; /* 4 : 3 */
else
avi_info_frame[5] |= 0x28; /* 16 : 9 */
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
checksum += avi_info_frame[i];
avi_info_frame[3] = 0x100 - checksum;
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
}
static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
int clk_div, int clk_double)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
int x, y;
/* Write clear interrupt status bits */
writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
if (sunxi_display.monitor == sunxi_monitor_hdmi)
sunxi_hdmi_setup_info_frames(mode);
/* Set input sync enable */
writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
/* Init various registers, select pll3 as clock source */
writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
/* Setup clk div and doubler */
clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
if (!clk_double)
setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
/* Setup timing registers */
writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
&hdmi->video_size);
x = mode->hsync_len + mode->left_margin;
y = mode->vsync_len + mode->upper_margin;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
x = mode->right_margin;
y = mode->lower_margin;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
x = mode->hsync_len;
y = mode->vsync_len;
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
}
static void sunxi_hdmi_enable(void)
{
struct sunxi_hdmi_reg * const hdmi =
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
udelay(100);
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
}
#endif /* CONFIG_VIDEO_HDMI */
#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_tvencoder_mode_set(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_tve_reg * const tve =
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
/* Reset off */
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
switch (sunxi_display.monitor) {
case sunxi_monitor_vga:
tvencoder_mode_set(tve, tve_mode_vga);
break;
case sunxi_monitor_composite_pal_nc:
tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
break;
case sunxi_monitor_composite_pal:
tvencoder_mode_set(tve, tve_mode_composite_pal);
break;
case sunxi_monitor_composite_pal_m:
tvencoder_mode_set(tve, tve_mode_composite_pal_m);
break;
case sunxi_monitor_composite_ntsc:
tvencoder_mode_set(tve, tve_mode_composite_ntsc);
break;
case sunxi_monitor_none:
case sunxi_monitor_dvi:
case sunxi_monitor_hdmi:
case sunxi_monitor_lcd:
break;
}
}
#endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
static void sunxi_drc_init(void)
{
#ifdef CONFIG_SUNXI_GEN_SUN6I
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* On sun6i the drc must be clocked even when in pass-through mode */
#ifdef CONFIG_MACH_SUN8I_A33
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
#endif
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
}
#ifdef CONFIG_VIDEO_VGA_VIA_LCD
static void sunxi_vga_external_dac_enable(void)
{
int pin;
pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
if (pin >= 0) {
gpio_request(pin, "vga_enable");
gpio_direction_output(pin, 1);
}
}
static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
bool for_ext_vga_dac)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
sunxi_gpio_set_drv(pin, 3);
#endif
}
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
/* Use tcon0 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
&lcdc->tcon0_timing_active);
bp = mode->hsync_len + mode->left_margin;
total = mode->xres + mode->right_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
&lcdc->tcon0_timing_sync);
writel(0, &lcdc->tcon0_hv_intf);
writel(0, &lcdc->tcon0_cpu_intf);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (sunxi_display.depth == 18) ? 1 : 0;
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf);
#endif
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
writel(((sunxi_display.depth == 18) ?
SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
&lcdc->tcon0_frm_ctrl);
}
val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
val |= SUNXI_LCDC_TCON_HSYNC_MASK;
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
val |= SUNXI_LCDC_TCON_VSYNC_MASK;
#ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
if (for_ext_vga_dac)
val = 0;
#endif
writel(val, &lcdc->tcon0_io_polarity);
writel(0, &lcdc->tcon0_io_tristate);
}
