int nand_dma_config_start(__u32 rw, dma_addr_t addr,__u32 length)
{
//int ret = 0;
//int nents = 0;
struct dma_slave_config dma_conf = {0};
struct dma_async_tx_descriptor *dma_desc = NULL;
dma_conf.direction = DMA_DEV_TO_MEM;
dma_conf.src_addr = 0x01c03300;
dma_conf.dst_addr = 0x01c03300;
dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.src_maxburst = 1;
dma_conf.dst_maxburst = 1;
dma_conf.slave_id = rw ? sunxi_slave_id(DRQDST_NAND0, DRQSRC_SDRAM) : sunxi_slave_id(DRQDST_SDRAM, DRQSRC_NAND0);
dmaengine_slave_config(dma_hdl, &dma_conf);
dma_desc = dmaengine_prep_slave_single(dma_hdl, addr, length,
(rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE), DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
if (!dma_desc) {
printk("dmaengine prepare failed!\n");
return -1;
}
dma_desc->callback = nand_dma_callback;
dma_desc->callback_param = NULL;
dmaengine_submit(dma_desc);
dma_async_issue_pending(dma_hdl);
return 0;
}
static int sunxi_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
struct sunxi_dma_params *dmap;
struct dma_slave_config slave_config;
int ret;
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ret = snd_hwparams_to_dma_slave_config(substream, params,
&slave_config);
if (ret) {
dev_err(dev, "hw params config failed with err %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.dst_addr = dmap->dma_addr;
slave_config.src_maxburst = 4;
slave_config.dst_maxburst = 4;
slave_config.slave_id = sunxi_slave_id(DRQDST_AUDIO_CODEC, DRQSRC_SDRAM);
} else {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.src_addr = dmap->dma_addr;
slave_config.src_maxburst = 4;
slave_config.dst_maxburst = 4;
slave_config.slave_id = sunxi_slave_id(DRQDST_SDRAM, DRQSRC_AUDIO_CODEC);
}
ret = dmaengine_slave_config(chan, &slave_config);
if (ret < 0) {
dev_err(dev, "dma slave config failed with err %d\n", ret);
return ret;
}
#if defined USED_SRAM_ADDR
/*for a23*/
#if defined CONFIG_ARCH_SUN8IW3
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
substream->dma_buffer.addr = 0x00002000;
substream->dma_buffer.area = 0xf0002000;
memset(0xf0002000, 0, 0x4000-0x00002000);
}
#endif
#endif
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int sunxi_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct device *dev = rtd->platform->dev;
struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
struct sunxi_dma_params *dmap;
struct dma_slave_config slave_config;
int ret;
dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
ret = snd_hwparams_to_dma_slave_config(substream, params,
&slave_config);
if (ret) {
dev_err(dev, "hw params config failed with err %d\n", ret);
return ret;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
slave_config.dst_addr = dmap->dma_addr;
slave_config.src_maxburst = 4;
slave_config.dst_maxburst = 4;
slave_config.slave_id = sunxi_slave_id(DRQDST_DAUDIO_0_TX, DRQSRC_SDRAM);
if (SNDRV_PCM_FORMAT_S16_LE == params_format(params)) {
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
} else {
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
}
} else {
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.src_addr = dmap->dma_addr;
slave_config.src_maxburst = 4;
slave_config.dst_maxburst = 4;
slave_config.slave_id = sunxi_slave_id(DRQDST_SDRAM, DRQSRC_DAUDIO_0_RX);
}
ret = dmaengine_slave_config(chan, &slave_config);
if (ret < 0) {
dev_err(dev, "dma slave config failed with err %d\n", ret);
return ret;
}
snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
return 0;
}
static int ss_dma_src_config(sunxi_ss_t *sss, void *ctx, ss_aes_req_ctx_t *req_ctx, int len, int cb)
{
int flow = ((ss_comm_ctx_t *)ctx)->flow;
ss_dma_info_t *info = &req_ctx->dma_src;
struct dma_slave_config dma_conf = {0};
struct dma_async_tx_descriptor *dma_desc = NULL;
info->dir = DMA_MEM_TO_MEM;
dma_conf.direction = info->dir;
#ifdef SS_CTR_MODE_ENABLE
if (req_ctx->mode == SS_AES_MODE_CTR)
dma_conf.src_addr_width = dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
else
#endif
dma_conf.src_addr_width = dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.src_maxburst = 1;
dma_conf.dst_maxburst = 1;
dma_conf.slave_id = sunxi_slave_id(DRQDST_SDRAM, DRQSRC_SDRAM);
dmaengine_slave_config(info->chan, &dma_conf);
ss_sg_table_init(&info->sgt_for_cp, info->sg, len, sss->flows[flow].buf_src, sss->flows[flow].buf_src_dma);
SS_DBG("chan: 0x%p, info->sgt_for_cp.sgl: 0x%p \n", info->chan, info->sgt_for_cp.sgl);
info->nents = info->sgt_for_cp.nents;
SS_DBG("flow: %d, sg num: %d, total len: %d \n", flow, info->nents, len);
dma_map_sg(&sss->pdev->dev, info->sg, info->nents, info->dir);
dma_map_sg(&sss->pdev->dev, info->sgt_for_cp.sgl, info->nents, info->dir);
if (SS_METHOD_IS_HASH(req_ctx->type)) {
/* Total len is to small, so there is no data for DMA. */
if (len < SHA1_BLOCK_SIZE)
return 1;
ss_hash_padding_sg_prepare(&info->sg[info->nents-1], len);
ss_hash_padding_sg_prepare(&info->sgt_for_cp.sgl[info->nents-1], len);
}
dma_desc = info->chan->device->device_prep_dma_sg(info->chan,
info->sgt_for_cp.sgl, info->nents,
info->sg, info->nents, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma_desc) {
SS_ERR("dmaengine_prep_slave_sg() failed!\n");
return -1;
}
if (cb == 1) {
dma_desc->callback = ss_dma_cb;
dma_desc->callback_param = (void *)req_ctx;
}
dmaengine_submit(dma_desc);
return 0;
}
/* ctx - only used for HASH. */
static int ss_dma_src_config(sunxi_ss_t *sss, void *ctx, ss_aes_req_ctx_t *req_ctx, int len, int cb)
{
int nents = 0;
int npages = 0;
ss_dma_info_t *info = &req_ctx->dma_src;
struct dma_slave_config dma_conf = {0};
struct dma_async_tx_descriptor *dma_desc = NULL;
info->dir = DMA_MEM_TO_DEV;
dma_conf.direction = info->dir;
dma_conf.dst_addr = sss->base_addr_phy + SS_REG_RXFIFO;
dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.src_maxburst = 1;
dma_conf.dst_maxburst = 1;
dma_conf.slave_id = sunxi_slave_id(DRQDST_SS, DRQSRC_SDRAM);
dmaengine_slave_config(info->chan, &dma_conf);
npages = ss_sg_cnt(info->sg, len);
WARN_ON(npages == 0);
nents = dma_map_sg(&sss->pdev->dev, info->sg, npages, info->dir);
SS_DBG("npages = %d, nents = %d, len = %d, sg.len = %d \n", npages, nents, len, sg_dma_len(info->sg));
if (!nents) {
SS_ERR("dma_map_sg() error\n");
return -EINVAL;
}
info->nents = nents;
if (SS_METHOD_IS_HASH(req_ctx->type)) {
ss_hash_padding_sg_prepare(&info->sg[nents-1], len);
/* Total len is too small, so there is no data for DMA. */
if (len < SHA1_BLOCK_SIZE)
return 1;
}
dma_desc = dmaengine_prep_slave_sg(info->chan, info->sg, nents,
info->dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma_desc) {
SS_ERR("dmaengine_prep_slave_sg() failed!\n");
return -1;
}
if (cb == 1) {
dma_desc->callback = ss_dma_cb;
dma_desc->callback_param = (void *)req_ctx;
}
dmaengine_submit(dma_desc);
return 0;
}
static int ss_dma_dst_config(sunxi_ss_t *sss, void *ctx, ss_aes_req_ctx_t *req_ctx, int len, int cb)
{
int nents = 0;
int npages = 0;
ss_dma_info_t *info = &req_ctx->dma_dst;
struct dma_slave_config dma_conf = {0};
struct dma_async_tx_descriptor *dma_desc = NULL;
info->dir = DMA_DEV_TO_MEM;
dma_conf.direction = info->dir;
dma_conf.src_addr = sss->base_addr_phy + SS_REG_TXFIFO;
dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_conf.src_maxburst = 1;
dma_conf.dst_maxburst = 1;
dma_conf.slave_id = sunxi_slave_id(DRQDST_SDRAM, DRQSRC_SS);
dmaengine_slave_config(info->chan, &dma_conf);
npages = ss_sg_cnt(info->sg, len);
WARN_ON(npages == 0);
nents = dma_map_sg(&sss->pdev->dev, info->sg, npages, info->dir);
SS_DBG("npages = %d, nents = %d, len = %d, sg.len = %d \n", npages, nents, len, sg_dma_len(info->sg));
if (!nents) {
SS_ERR("dma_map_sg() error\n");
return -EINVAL;
}
info->nents = nents;
dma_desc = dmaengine_prep_slave_sg(info->chan, info->sg, nents,
info->dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!dma_desc) {
SS_ERR("dmaengine_prep_slave_sg() failed!\n");
return -1;
}
if (cb == 1) {
dma_desc->callback = ss_dma_cb;
dma_desc->callback_param = (void *)req_ctx;
}
dmaengine_submit(dma_desc);
return 0;
}
static int i2s_set_dma_daudio0_to_hdmi(int on)
{
int ret;
if (on) {
struct dma_slave_config slave_config;
down_prtdma = kzalloc(sizeof(*down_prtdma), GFP_KERNEL);
if (!down_prtdma)
return -ENOMEM;
ret = snd_dmaengine_pcm_open_diy(down_prtdma, NULL, NULL);
if (ret) {
printk("<0> upstream dmaengine pcm open failed with err %d\n", ret);
return ret;
}
slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
slave_config.dst_addr = 0x01c22820;//hdmi tx addr
slave_config.src_addr = 0x01c22010;//daudio0 rx addr
slave_config.direction = DMA_DEV_TO_DEV;
slave_config.src_maxburst = 4;
slave_config.dst_maxburst = 4;
slave_config.slave_id = sunxi_slave_id(DRQDST_DAUDIO_2_TX, DRQSRC_DAUDIO_0_RX);//dst=daudio2-hdmiaudio,src=daudio0
ret = dmaengine_slave_config(down_prtdma->dma_chan, &slave_config);
if (ret < 0) {
printk("<0> dma slave config failed with err %d\n", ret);
return ret;
}
snd_dmaengine_pcm_trigger_diy(down_prtdma, SNDRV_PCM_TRIGGER_START, 0, slave_config.direction, 1024, 512);
} else {
if (!down_prtdma) {
printk("<0> function:%s, down_prtdma = null !!!!\n",__func__);
return -ENOMEM;
}
snd_dmaengine_pcm_trigger_diy(down_prtdma, SNDRV_PCM_TRIGGER_STOP, 0, 0, 1024, 512);
snd_dmaengine_pcm_close_diy(down_prtdma);
kfree(down_prtdma);
}
return 0;
}
