void
main(void)
{
memset(edata, 0, (ulong)end-(ulong)edata);
conf.nmach = 1;
machinit();
confinit();
xinit();
trapinit();
mmuinit();
plan9iniinit();
hwintrinit();
clockinit();
timerinit();
console();
quotefmtinstall();
printinit();
cpuidprint();
print("\nPlan 9 from Bell Labs\n");
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
sharedseginit();
fpsave(&initfp);
initfp.fpscr = 0;
userinit();
schedinit();
}
void
main(void)
{
cgapost(0);
mach0init();
options();
ioinit();
i8250console();
quotefmtinstall();
screeninit();
print("\nPlan 9\n");
trapinit0();
mmuinit0();
kbdinit();
i8253init();
cpuidentify();
meminit();
confinit();
archinit();
if(!isa20on())
panic("bootstrap didn't leave a20 address line enabled");
xinit();
if(i8237alloc != nil)
i8237alloc();
trapinit();
printinit();
cpuidprint();
mmuinit();
fpsavealloc();
if(arch->intrinit) /* launches other processors on an mp */
arch->intrinit();
timersinit();
mathinit();
kbdenable();
if(arch->clockenable)
arch->clockenable();
procinit0();
initseg();
if(delaylink){
bootlinks();
pcimatch(0, 0, 0);
}else
links();
conf.monitor = 1;
chandevreset();
cgapost(0xcd);
pageinit();
i8253link();
swapinit();
userinit();
active.thunderbirdsarego = 1;
cgapost(0x99);
schedinit();
}
void
main(void)
{
extern char edata[], end[];
uint rev;
okay(1);
m = (Mach*)MACHADDR;
memset(edata, 0, end - edata); /* clear bss */
machinit();
mmuinit1();
optionsinit("/boot/boot boot");
quotefmtinstall();
ataginit((Atag*)BOOTARGS);
confinit(); /* figures out amount of memory */
xinit();
uartconsinit();
screeninit();
print("\nPlan 9 from Bell Labs\n");
rev = getfirmware();
print("firmware: rev %d\n", rev);
if(rev < Minfirmrev){
print("Sorry, firmware (start.elf) must be at least rev %d (%s)\n",
Minfirmrev, Minfirmdate);
for(;;)
;
}
trapinit();
clockinit();
printinit();
timersinit();
cpuidprint();
archreset();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
pageinit();
swapinit();
userinit();
gpiomeminit();
schedinit();
assert(0); /* shouldn't have returned */
}
void
main(void)
{
hwrpb = (Hwrpb*)0x10000000;
hwrpb = (Hwrpb*)(KZERO|hwrpb->phys);
arginit();
machinit();
options();
ioinit();
clockinit();
confinit();
archinit();
xinit();
memholes();
if(i8237alloc != nil)
i8237alloc();
mmuinit();
if(arch->coreinit)
arch->coreinit();
trapinit();
screeninit();
printinit();
/* it's now safe to print */
/* dumpopts(); /* DEBUG */
i8250console();
quotefmtinstall();
print("\nPlan 9\n");
cpuidprint();
if(arch->corehello)
arch->corehello();
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
savefpregs(&initfp);
initfp.fpstatus = 0x68028000;
userinit();
schedinit();
}
void
main(void)
{
mmuinvalidate();
/* zero out bss */
memset(edata, 0, end-edata);
/* point to Mach structure */
m = (Mach*)MACHADDR;
memset(m, 0, sizeof(Mach));
m->ticks = 1;
active.machs = 1;
rs232power(1);
quotefmtinstall();
iprint("\nPlan 9 bitsy kernel\n");
confinit();
xinit();
mmuinit();
machinit();
trapinit();
sa1110_uartsetup(1);
dmainit();
screeninit();
printinit(); /* from here on, print works, before this we need iprint */
clockinit();
procinit0();
initseg();
links();
chandevreset();
pageinit();
swapinit();
userinit();
powerinit();
schedinit();
}
void
main(u32int ax, u32int bx)
{
vlong hz;
memset(edata, 0, end - edata);
/*
* ilock via i8250enable via i8250console
* needs m->machno, sys->machptr[] set, and
* also 'up' set to nil.
*/
cgapost(sizeof(uintptr)*8);
memset(m, 0, sizeof(Mach));
m->machno = 0;
m->online = 1;
m->nixtype = NIXTC;
sys->machptr[m->machno] = &sys->mach;
m->stack = PTR2UINT(sys->machstk);
m->vsvm = sys->vsvmpage;
up = nil;
active.nonline = 1;
active.exiting = 0;
active.nbooting = 0;
asminit();
multiboot(ax, bx, 0);
options(oargc, oargv);
crapoptions();
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
cgainit();
i8250console("0");
consputs = cgaconsputs;
vsvminit(MACHSTKSZ, NIXTC);
conf.nmach = 1;
fmtinit();
print("\nNIX\n");
if(vflag){
print("&ax = %#p, ax = %#ux, bx = %#ux\n", &ax, ax, bx);
multiboot(ax, bx, vflag);
}
m->perf.period = 1;
if((hz = archhz()) != 0ll){
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
}
/*
* Mmuinit before meminit because it
* flushes the TLB via m->pml4->pa.
*/
mmuinit();
ioinit();
kbdinit();
meminit();
confinit();
archinit();
mallocinit();
/*
* Acpiinit will cause the first malloc
* call to happen.
* If the system dies here it's probably due
* to malloc not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*/
acpiinit();
umeminit();
trapinit();
printinit();
/*
* This is necessary with GRUB and QEMU.
* Without it an interrupt can occur at a weird vector,
* because the vector base is likely different, causing
* havoc. Do it before any APIC initialisation.
*/
i8259init(32);
procinit0();
mpsinit(maxcores);
apiconline();
sipi();
timersinit();
kbdenable();
fpuinit();
psinit(conf.nproc);
initimage();
links();
devtabreset();
pageinit();
swapinit();
userinit();
nixsquids();
testiccs();
print("schedinit...\n");
schedinit();
}
/*
* entered from l.s with mmu enabled.
*
* we may have to realign the data segment; apparently 5l -H0 -R4096
* does not pad the text segment. on the other hand, we may have been
* loaded by another kernel.
*
* be careful not to touch the data segment until we know it's aligned.
*/
void
main(Mach* mach)
{
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
m = mach;
if (vfy != 0xcafebabe)
memmove(bdata, etext, edata - bdata);
if (vfy != 0xcafebabe) {
wave('?');
panic("misaligned data segment");
}
memset(edata, 0, end - edata); /* zero bss */
vfy = 0;
wave('9');
machinit();
archreset();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
archconsole();
wave(' ');
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* set memsize before xinit */
confinit();
/* xinit would print if it could */
xinit();
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockintr) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
trapinit();
clockinit();
printinit();
uartkirkwoodconsole();
/* only now can we print */
print("from Bell Labs\n\n");
#ifdef CRYPTOSANDBOX
print("sandbox: 64K at physical %#lux, mapped to 0xf10b0000\n",
PADDR((uintptr)sandbox & ~(BY2PG-1)));
#endif
archconfinit();
cpuidprint();
timersinit();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
spiprobe();
pageinit();
swapinit();
userinit();
schedinit();
panic("schedinit returned");
}
/*
* at entry, l.s has set m for cpu0 and printed "Plan 9 from Be"
* but has not zeroed bss.
*/
void
main(void)
{
int cpu;
static ulong vfy = 0xcafebabe;
up = nil;
if (vfy != 0xcafebabe) {
serialputc('?');
serialputc('d');
panic("data segment misaligned");
}
memset(edata, 0, end - edata);
/*
* we can't lock until smpon has run, but we're supposed to wait
* until l1 & l2 are on. too bad. l1 is on, l2 will soon be.
*/
smpon();
iprint("ll Labs ");
cacheinit();
/*
* data segment is aligned, bss is zeroed, caches' characteristics
* are known. begin initialisation.
*/
mach0init();
l2pageinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* l2 looks for *l2off= in plan9.ini */
l2cache->on(); /* l2->on requires locks to work, thus smpon */
l2cache->info(&cachel[2]);
allcache->on();
cortexa9cachecfg();
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(100);
navailcpus = getncpus();
iprint("(mp arm; %d cpus)\n\n", navailcpus);
delay(100);
for (cpu = 1; cpu < navailcpus; cpu++)
stopcpu(cpu);
xinit();
irqtooearly = 0; /* now that xinit and trapinit have run */
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* cfg clock signals, print cache cfg */
clockinit(); /* start clocks */
timersinit();
delay(50); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
chkmissing();
procinit0();
initseg();
// dmainit();
links();
conf.monitor = 1;
// screeninit();
iprint("pcireset...");
pcireset(); /* this tends to hang after a reboot */
iprint("ok\n");
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit(); /* prints "1020M memory: ⋯ */
swapinit();
userinit();
/*
* starting a cpu will eventually result in it calling schedinit,
* so everything necessary to run user processes should be set up
* before starting secondary cpus.
*/
launchinit();
/* SMP & FW are already on when we get here; u-boot set them? */
for (cpu = 1; cpu < navailcpus; cpu++)
if (startcpu(cpu) < 0)
panic("cpu%d didn't start", cpu);
l1diag();
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
monitor_clear();
xylos_logo();
kinit1(end, P2V(4 * 1024 * 1024)); // phys page allocator, 16MB for kernel
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("Initializing interrupts... ");
init_generic_irq_table();
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing console and serial... ");
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Setting up swap space disk... ");
swapinit();
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing tasking... ");
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing pipe IPC... ");
init_pipe_ipc_system();
if(pipe_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Initializing direct IPC... ");
init_direct_ipc_table();
if(direct_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Mounting root filesystem... ");
fileinit(); // file table
ideinit(); // disk
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
if(!ismp) {
cprintf("Starting up uniprocessor CPU... ");
timerinit(); // uniprocessor timer
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
if(ismp) {
if(ncpu > 1) {
cprintf("Starting up %d CPU cores... ", ncpu);
} else {
cprintf("Starting up %d CPU core... ", ncpu);
}
}
startothers(); // start other processors
kinit2(P2V(4 * 1024 * 1024), P2V(PHYSTOP)); // 16MB to PHYSTOP [234MB]
if(ismp) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
// detects and starts km drivers
auto_enable_nic();
// first user process
userinit();
// Finish setting up this processor in mpmain.
mpmain();
}
void
main(uint32_t mbmagic, uint32_t mbaddress)
{
Mach *m = entrym;
/* when we get here, entrym is set to core0 mach. */
sys->machptr[m->machno] = m;
// Very special case for BSP only. Too many things
// assume this is set.
wrmsr(GSbase, PTR2UINT(&sys->machptr[m->machno]));
if (machp() != m)
panic("m and machp() are different!!\n");
assert(sizeof(Mach) <= PGSZ);
/*
* Check that our data is on the right boundaries.
* This works because the immediate value is in code.
*/
if (x != 0x123456)
panic("Data is not set up correctly\n");
memset(edata, 0, end - edata);
m = (void *) (KZERO + 1048576 + 11*4096);
sys = (void *) (KZERO + 1048576);
/*
* ilock via i8250enable via i8250console
* needs m->machno, sys->machptr[] set, and
* also 'up' set to nil.
*/
cgapost(sizeof(uintptr_t)*8);
memset(m, 0, sizeof(Mach));
m->machno = 0;
m->online = 1;
m->nixtype = NIXTC;
sys->machptr[m->machno] = &sys->mach;
m->stack = PTR2UINT(sys->machstk);
*(uintptr_t*)m->stack = STACKGUARD;
m->vsvm = sys->vsvmpage;
m->externup = (void *)0;
active.nonline = 1;
active.exiting = 0;
active.nbooting = 0;
asminit();
multiboot(mbmagic, mbaddress, 0);
options(oargc, oargv);
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
cgainit();
i8250console("0");
consputs = cgaconsputs;
/* It all ends here. */
vsvminit(MACHSTKSZ, NIXTC, m);
if (machp() != m)
panic("After vsvminit, m and machp() are different");
sys->nmach = 1;
fmtinit();
print("\nHarvey\n");
if(vflag){
multiboot(mbmagic, mbaddress, vflag);
}
m->perf.period = 1;
if((hz = archhz()) != 0ll){
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
}
//iprint("archhz returns 0x%lld\n", hz);
//iprint("NOTE: if cpuidhz runs too fast, we get die early with a NULL pointer\n");
//iprint("So, until that's fixed, we bring up AP cores slowly. Sorry!\n");
/*
* Mmuinit before meminit because it
* flushes the TLB via m->pml4->pa.
*/
mmuinit();
ioinit();
meminit();
confinit();
archinit();
mallocinit();
/* test malloc. It's easier to find out it's broken here,
* not deep in some call chain.
* See next note.
*
void *v = malloc(1234);
hi("v "); put64((uint64_t)v); hi("\n");
free(v);
hi("free ok\n");
*/
/*
* Acpiinit will cause the first malloc
* call to happen.
* If the system dies here it's probably due
* to malloc not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*/
if (0){ acpiinit(); hi(" acpiinit();\n");}
umeminit();
trapinit();
/*
* This is necessary with GRUB and QEMU.
* Without it an interrupt can occur at a weird vector,
* because the vector base is likely different, causing
* havoc. Do it before any APIC initialisation.
*/
i8259init(32);
procinit0();
mpsinit(maxcores);
apiconline();
/* Forcing to single core if desired */
if(!nosmp) {
sipi();
}
teardownidmap(m);
timersinit();
fpuinit();
psinit(conf.nproc);
initimage();
links();
keybinit();
keybenable();
mouseenable();
devtabreset();
pageinit();
swapinit();
userinit();
/* Forcing to single core if desired */
if(!nosmp) {
nixsquids();
testiccs();
}
print("CPU Freq. %dMHz\n", m->cpumhz);
print("schedinit...\n");
schedinit();
}
void
main(void)
{
int machno;
/* entry to main pushed stuff onto the stack. */
// memset(edata, 0, (ulong)end-(ulong)edata);
machno = getpir();
if (machno > 0)
startcpu(machno);
// dcrcompile();
if (dverify != 0x01020304) {
uartlputs("data segment not initialised\n");
panic("data segment not initialised");
}
if (bverify != 0) {
uartlputs("bss segment not zeroed\n");
panic("bss segment not zeroed");
}
mach0init();
archreset();
quotefmtinstall();
optionsinit("/boot/boot boot");
// archconsole();
meminit();
confinit();
mmuinit();
xinit(); /* xinit would print if it could */
trapinit();
qtminit();
ioinit();
uncinit();
printinit();
uartliteconsole();
mainmem->flags |= POOL_ANTAGONISM;
mainmem->panic = mypanic;
ethermedium.maxtu = 1512; /* must be multiple of 4 for temac's dma */
// print("\n\nPlan 9k H\n"); /* already printed by l.s */
plan9iniinit();
timersinit();
clockinit();
dma0init(); /* does not start kprocs; see init0 */
fpuinit();
procinit0();
initseg();
links();
chandevreset();
okprint = 1; /* only now can we print */
barriers();
dcflush((uintptr)&okprint, sizeof okprint);
cpuidprint();
print("%d Hz clock", HZ);
print("; memory size %,ud (%#ux)\n", (uint)memsz, (uint)memsz);
pageinit();
swapinit();
userinit();
active.thunderbirdsarego = 1;
dcflush((uintptr)&active.thunderbirdsarego,
sizeof active.thunderbirdsarego);
schedinit();
/* no return */
panic("schedinit returned");
}
void
main(void)
{
// int i;
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
/* l.s has already printed "Plan 9 from Be" */
// m = mach; /* now done in l.s */
/* realign data seg; apparently -H0 -R4096 does not pad the text seg */
if (vfy != 0xcafebabe) {
// wave('<'); wave('-');
memmove(bdata, etext, edata - bdata);
}
/*
* once data segment is in place, always zero bss since we may
* have been loaded by another Plan 9 kernel.
*/
memset(edata, 0, end - edata); /* zero BSS */
cacheuwbinv();
l2cacheuwbinv();
if (vfy != 0xcafebabe)
panic("data segment misaligned");
vfy = 0;
wave('l');
machinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(500);
iprint("l Labs\n\n");
delay(500);
xinit();
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* configure clock signals */
clockinit(); /* start clocks */
timersinit();
watchdoginit();
delay(250); /* let uart catch up */
printinit();
// kbdenable();
cpuidprint();
// chkmissing();
procinit0();
initseg();
dmainit();
links();
conf.monitor = 1;
screeninit();
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit();
swapinit();
userinit();
schedinit();
}