/*----------------------------------------------------------------------------*/
static enum Result streamInit(void *object, const void *configBase)
{
const struct DmaBaseConfig * const config = configBase;
struct DmaBase * const stream = object;
assert(config->stream < ARRAY_SIZE(instances));
assert(config->priority < 4);
const unsigned int controller = config->stream >= DMA1_STREAM_COUNT;
const unsigned int number = controller ?
config->stream - DMA1_STREAM_COUNT : config->stream;
if (controller == 0)
{
assert(number < 7);
stream->reg = STM_DMA1->CHANNELS + number;
stream->irq = DMA1_CHANNEL1_IRQ + number;
if (!sysClockStatus(CLK_DMA1))
sysClockEnable(CLK_DMA1);
}
else
{
assert(number < 5);
stream->reg = STM_DMA2->CHANNELS + number;
stream->irq = DMA2_CHANNEL1_IRQ + number;
if (!sysClockStatus(CLK_DMA2))
sysClockEnable(CLK_DMA2);
}
stream->config = CCR_PL(config->priority);
stream->handler = 0;
stream->number = config->stream;
switch (config->type)
{
case DMA_TYPE_M2M:
stream->config |= CCR_MEM2MEM;
break;
case DMA_TYPE_M2P:
stream->config |= CCR_DIR;
break;
default:
break;
}
return E_OK;
}
/*----------------------------------------------------------------------------*/
static enum result eepromInit(void *object, const void *configBase)
{
const struct EepromConfig * const config = configBase;
struct Eeprom * const interface = object;
if (!setDescriptor(0, interface))
return E_BUSY;
interface->position = 0;
interface->size = (uintptr_t)&_eeeprom - (uintptr_t)&_seeprom;
interface->blocking = true;
/* Enable clock to register interface and peripheral */
sysClockEnable(CLK_M4_EEPROM);
/* Reset registers to default values */
sysResetEnable(RST_EEPROM);
const uint32_t frequency = clockFrequency(MainClock);
LPC_EEPROM->CLKDIV = (frequency + (EEPROM_CLOCK - 1)) / EEPROM_CLOCK - 1;
LPC_EEPROM->INTENSET = INT_PROG_DONE;
if (config)
irqSetPriority(EEPROM_IRQ, config->priority);
irqEnable(EEPROM_IRQ);
return E_OK;
}
/*----------------------------------------------------------------------------*/
void platformStartup(void)
{
sysClockDisable(CLK_SSP0);
/* Enable clock for IOCON block, clock for GPIO is enabled by default */
sysClockEnable(CLK_IOCON);
}
/*----------------------------------------------------------------------------*/
void platformStartup(void)
{
static const enum SysClockBranch clocksToEnable[] = {
CLK_AFIO
};
for (size_t index = 0; index < ARRAY_SIZE(clocksToEnable); ++index)
sysClockEnable(clocksToEnable[index]);
}
/*----------------------------------------------------------------------------*/
static enum Result pinInterruptInit(void *object, const void *configBase)
{
const struct PinInterruptConfig * const config = configBase;
assert(config);
const struct Pin input = pinInit(config->pin);
assert(pinValid(input));
/* Try to allocate a new channel */
struct PinInterrupt * const interrupt = object;
const int channel = setInstance(interrupt);
if (channel == -1)
return E_BUSY;
/* Configure the pin */
pinInput(input);
pinSetPull(input, config->pull);
interrupt->callback = 0;
interrupt->channel = channel;
interrupt->enabled = false;
interrupt->event = config->event;
interrupt->pin = input.data;
const uint8_t index = interrupt->channel >> 2;
const uint32_t mask = 1UL << interrupt->channel;
/* Enable peripheral */
if (!sysClockStatus(CLK_PINT))
sysClockEnable(CLK_PINT);
/* Select pin and port */
LPC_SYSCON->PINTSEL[index] =
(LPC_SYSCON->PINTSEL[index] & ~PINTSEL_CHANNEL_MASK(channel))
| PINTSEL_CHANNEL(channel, input.data.port, input.data.offset);
/* Configure interrupt as edge sensitive */
LPC_GPIO_INT->ISEL &= ~mask;
/* Configure edge sensitivity options */
if (config->event == PIN_RISING || config->event == PIN_TOGGLE)
LPC_GPIO_INT->SIENR = mask;
if (config->event == PIN_FALLING || config->event == PIN_TOGGLE)
LPC_GPIO_INT->SIENF = mask;
#ifdef CONFIG_PM
/* Interrupt will wake the controller from low-power modes */
LPC_SYSCON->STARTERP0 |= STARTERP0_PINT(interrupt->channel);
#endif
/* Configure interrupt priority, interrupt is disabled by default */
irqSetPriority(calcVector(interrupt->channel), config->priority);
return E_OK;
}
int my_usrRoot(char* pMemPoolStart, unsigned int memPoolSize) {
eventLibInit();
semBLibInit();
semMLibInit();
semCLibInit();
semQLibInit();
wdLibInit();
taskHookInit();
memInit(pMemPoolStart, memPoolSize);
memPartLibInit(pMemPoolStart, memPoolSize);
if (proc_sysMmuLibInit == 0)
goto usrRoot_failed;
int (*_sysMmuLibInit)() = (void*) proc_sysMmuLibInit;
if (_sysMmuLibInit(0x1000) != 0)
goto usrRoot_failed;
if (vmMpuLibInit(0x1000) != 0)
goto usrRoot_failed;
if (vmBaseGlobalMapInit(&MemDescArray, MemDescArrayCount, 1) == 0)
goto usrRoot_failed;
sysClockConnect(usrClock, 0);
sysClockRateSet(60);
sysClockEnable();
selectInit(50);
usrBootLineParse(0x1000);
iosInit(20, 50, "/null");
ttyDrv();
usrSerialInit();
hashLibInit();
envLibInit(1);
sigInit();
excInit();
logInit(fdConsole, 50);
stdioInit();
fioLibInit();
selTaskDeleteHookAdd();
sub_FFB5F728();
my_taskcreate_Startup();
return 0;
usrRoot_failed:
printExc("usrRoot: MMU configuration failed, errno = %#x", *(long*) (GetErrorNumAddr()), 0, 0, 0, 0);
reboot(1);
return 0;
}
