void pwr_set_clk_profile(int profile)
{
int i, ticks;
int old;
if(profile > sizeof(clk_profile)/sizeof(w99702_clk_t)) return;
cyg_scheduler_lock();
//HAL_DISABLE_INTERRUPTS(old);
sysDisableCache();
sysInvalidCache();
sysFlushCache(I_D_CACHE);
sysEnableCache(CACHE_WRITE_BACK);
//outpw(0x3FFF001C, inpw(0x3FFF001C)|0xC);
//outpw(0x7FF00108, (inpw(0x7FF00108)&(~3))|0x2);
pwr_set_clk(&clk_profile[profile]);
current_clk_profile = profile;
//HAL_RESTORE_INTERRUPTS(old);
cyg_scheduler_unlock();
}
/*-----------------------------------------------------------------------------*/
int main(void)
{
int i, chr;
sysDisableCache();
sysFlushCache(I_D_CACHE);
sysEnableCache(CACHE_WRITE_BACK);
sysInitializeUART();
/* enable MTP clock */
outpw(REG_CLK_PCLKEN1, inpw(REG_CLK_PCLKEN1) | (1 << 26));
i = 0;
while (1)
{
sysprintf("+-------------------------------------------+\n");
sysprintf("| MTP menu |\n");
sysprintf("+-------------------------------------------+\n");
sysprintf("| [1] On-chip MTP key status |\n");
sysprintf("| [2] Program MTP key |\n");
sysprintf("| [3] Lock MTP key |\n");
sysprintf("+-------------------------------------------+\n");
chr = sysGetChar();
switch (chr)
{
case '1':
if (MTP_Enable() != MTP_RET_OK)
{
sysprintf("Failed to enable MTP!\n");
break;
}
dump_mtp_status();
break;
case '2':
if (MTP_Program(key_table[i++], 0x40) == MTP_RET_OK)
sysprintf("MTP key program done.\n");
else
sysprintf("Failed to program MTP key!\n");
break;
case '3':
if (MTP_Lock() == MTP_RET_OK)
sysprintf("MTP key is locked.\n");
else
sysprintf("Failed to lock MTP key!\n");
break;
}
sysprintf("\nPress any key...\n");
sysGetChar();
}
}
int sysInit (void)
{
/* <0> Save threads debug entry. */
#ifndef ECOS
{
extern UCHAR ASM_THREADS_DUMP_FUN[]; //A buffer in wb_init.s
UINT32 uThreadDebugFun_Addr = (UINT32) &tt_dump_threads;
memcpy (ASM_THREADS_DUMP_FUN, &uThreadDebugFun_Addr, sizeof (UINT32));
}
#endif
/* <1> Enable flash. */
sysFlushCache (I_D_CACHE);
sysDisableCache ();
sysEnableCache (CACHE_WRITE_BACK);
/* <2> Disable almost all of the engines for safety. */
outpw (REG_CLKCON, inpw (REG_CLKCON) | CPUCLK_EN | APBCLK_EN | HCLK2_EN);
outpw (REG_CLKSEL, SYSTEM_CLK_FROM_XTAL);
outpw (REG_APLLCON, PLL_OUT_OFF);
outpw (REG_UPLLCON, PLL_OUT_OFF);
/* <3> Initialize UART. */
/*
{
WB_UART_T uart;
TURN_ON_UART_CLOCK;
uart.uiFreq = OPT_XIN_CLOCK;
uart.uiBaudrate = 57600;
uart.uiDataBits = WB_DATA_BITS_8;
uart.uiStopBits = WB_STOP_BITS_1;
uart.uiParity = WB_PARITY_NONE;
uart.uiRxTriggerLevel = LEVEL_1_BYTE;
sysInitializeUART(&uart);
printf ("UART ok\n");
}
*/
/* <4> Set PLL. */
// SDRAM MCLK automatically on/off
outpw(REG_SDICON, inpw(REG_SDICON) & 0xBFFFFFFF);
// Force MPEG4 transfer length as 8 bytes
outpw(REG_BBLENG1, (inpw(REG_BBLENG1) & 0xFFFFFFF8) | 0x2);
// CLKDIV0
// Bit 1~0 : APB = HCLK1/? -------------------------+
// Bit15~8 : VPOST = PLL/? -----------------------+ |
// Bit19~16: USB = PLL/? ---------------------+ | |
// Bit23~20: Audio = PLL/? --------------------+| | |
// Bit27~24: Sensor = PLL/? -------------------+|| | |
// Bit31~28: System = PLL/? ------------------+||| | |
// |||| | |
// ||||++ |
// outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0x0fc|0x01322302); //(ok for 108)
#ifndef ECOS
outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0x0fc|0x25362401); //(ok for 336(112))
#else
//outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0xf00000fc|0x05362401); //can't modify system clock
outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0x0fc|0x25362401); //(ok for 336(112))
#endif
// outpw(REG_CLKDIV0, inpw(REG_CLKDIV0)&0x0fc|0x03331802); //(ok for 144)
//Adjust SDRAM
printf("setting apll to 0x%x, upll to 0x%x\n", pllEvalPLLCON (OPT_XIN_CLOCK, OPT_APLL_OUT_CLOCK), pllEvalPLLCON (OPT_XIN_CLOCK, OPT_UPLL_OUT_CLOCK));
outpw(REG_APLLCON, pllEvalPLLCON (OPT_XIN_CLOCK, OPT_APLL_OUT_CLOCK));
outpw(REG_UPLLCON, pllEvalPLLCON (OPT_XIN_CLOCK, OPT_UPLL_OUT_CLOCK));
// +-------- Bit31~28 : HCLK (from system)
// |+------- Bit27~24 : CPU (from HCLK)
// ||+------ Bit23~20 : HCLK1 (from HCLK, must less or equal to HCLK and CPU)
// |||+----- Bit19~16 : HCLK2 (from HCLK)
// ||||+---- Bit15~12 : MPEG4, JPEG (from HCLK2)
// |||||+--- Bit11~8 : 2D, VPE (from HCLK2)
// ||||||+-- Bit 7~6 : DSP (from HCLK2)
// |||||||+- Bit 5~0 : Reserved.
// outpw(REG_CLKDIV1, 0x00105045); //(ok for 108)
outpw(REG_CLKDIV1, 0x00105045); //(ok for 112)
// outpw(REG_CLKDIV1, 0x00110005);
#ifndef ECOS //don't need to modify system clock source
outpw(REG_CLKSEL, SYSTEM_CLK_FROM_UPLL);
#endif
printf("before system clock\n");
outpw(REG_CLKSEL, SYSTEM_CLK_FROM_UPLL);
printf("system clock ok\n");
/* <5> Initialize TinyThread to support multi-thread. */
#ifndef ECOS
tt_init (OPT_XIN_CLOCK, OPT_UPLL_OUT_CLOCK);
#else
//tt_init (OPT_XIN_CLOCK, OPT_UPLL_OUT_CLOCK);
printf("reg_tcr0=0x%x reg_ticr0=0x%x\n", inpw(REG_TCR0), inpw(REG_TICR0));
printf("reg_tcr1=0x%x reg_ticr1=0x%x\n", inpw(REG_TCR1), inpw(REG_TICR1));
#endif
/* <6> Set other engine clocks. */
/* Set vpost clock:
Why I can NOT call it after HIC is transferred. */
outpw (REG_CLKSEL, inpw (REG_CLKSEL) | VIDEO_CLK_FROM_UPLL);
tt_msleep (30);
TURN_ON_VPOST_CLOCK;
tt_msleep (30);
/* Set audio clock. */
outpw (REG_CLKSEL, inpw (REG_CLKSEL) | AUDIO_CLK_FROM_APLL);
tt_msleep (30);
TURN_ON_AUDIO_CLOCK;
tt_msleep (30);
/* Set sensor clock. */
outpw (REG_CLKSEL, inpw (REG_CLKSEL) | SENSOR_CLK_FROM_UPLL);
//tt_msleep (30);
//TURN_ON_DSP_CLOCK;
//tt_msleep (30);
//TURN_ON_CAP_CLOCK;
/* Set MP4 clock. */
//TURN_ON_MPEG4_CLOCK;
//tt_msleep (30);
/* Set VPE and 2D clock. */
TURN_ON_VPE_CLOCK;
tt_msleep (30);
TURN_ON_GFX_CLOCK;
tt_msleep (30);
/* Set USB clock */
#if 0
writew(REG_SYS_CFG, readw(REG_SYS_CFG)&0xffffffbf);
outpw (REG_CLKSEL, inpw (REG_CLKSEL) | USB_CLK_FROM_UPLL);
tt_msleep (30);
TURN_ON_USB_CLOCK;
outpw(REG_GPIO_PE,inpw(REG_GPIO_PE)|0x00000200);//GPIO9,disable pull-up or pull-down
#endif
return 0;
}
int main(void)
{
/* <1> Enable flash. */
sysFlushCache (I_D_CACHE);
sysDisableCache ();
sysEnableCache (CACHE_WRITE_BACK);
sysInit();
printf("REG_APLLCON=0x%x REG_UPLLCON=0x%x\n", inpw(REG_APLLCON), inpw(REG_UPLLCON));
printf("REG_CLKCON=0x%x REG_CLKSEL=0x%x\n", inpw(REG_CLKCON), inpw(REG_CLKSEL));
printf("REG_CLKDIV0=0x%x REG_CLKDIV1=0x%x\n", inpw(REG_CLKDIV0), inpw(REG_CLKDIV1));
printf("REG_TICR0=%d\n", inpw(REG_TICR0));
FTH_Init();
#if 0
test_inet(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_gethost(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_socket(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netread();
test_netwrite();
test_send();
test_recv();
test_recvmsg();
test_sendmsg();
test_recvfrom(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_sendto(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netselect();
test_getsockname();
test_getsockopt(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netfcntl(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netioctl(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netioctl_withbuf(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_wb740getgateway(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_wb740reboot(g_RemoteNet_Buf, RNT_BUFFER_LEN);
#endif
test_inet(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_gethost(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_socket(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netread();
test_netwrite();
test_send();
test_recv();
test_recvmsg();
test_sendmsg();
test_recvfrom(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_sendto(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netselect();
test_getsockname();
test_getsockopt(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netfcntl(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netioctl(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_netioctl_withbuf(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_wb740getgateway(g_RemoteNet_Buf, RNT_BUFFER_LEN);
test_wb740reboot(g_RemoteNet_Buf, RNT_BUFFER_LEN);
// insert test program here
//GetDevInterface();
//simple_getgateway();
//simple_ioctl_withbuf();
//simple_udpserver();
//simple_tcpserver();
//simple_inet_addr();
//simple_uname();
//simple_gethostbyaddr();
//simple_multi_thread();
//wb740reboot(g_RemoteNet_Buf, RNT_BUFFER_LEN);
return 0;
}
int main(void)
{
int32_t i32Err;
sysDisableCache();
sysFlushCache(I_D_CACHE);
sysEnableCache(CACHE_WRITE_BACK);
sysInitializeUART();
sysprintf("+-------------------------------------------------+\n");
sysprintf("| GPIO Sample Code |\n");
sysprintf("+-------------------------------------------------+\n\n");
/* Configure Port C to input mode and pull-up */
GPIO_Open(GPIOC, DIR_INPUT, PULL_UP);
/* Set Port C output data to 0xFFF */
GPIO_Set(GPIOC, 0xFFF);
/* Set Port C output data to 0x000 */
GPIO_Clr(GPIOC, 0xFFF);
/* Configure Port C to default value */
GPIO_Close(GPIOC);
i32Err = 0;
sysprintf("GPIO PD.3(output mode) connect to PD.4(input mode) ......");
/* Configure PD3 to output mode */
GPIO_OpenBit(GPIOD, BIT3, DIR_OUTPUT, NO_PULL_UP);
/* Configure PD4 to output mode */
GPIO_OpenBit(GPIOD, BIT4, DIR_INPUT, NO_PULL_UP);
/* Use Pin Data Input/Output Control to pull specified I/O or get I/O pin status */
/* Pull PD.3 to High and check PD.4 status */
GPIO_SetBit(GPIOD, BIT3);
if(GPIO_ReadBit(GPIOD,BIT4)==0)
i32Err = 1;
/* Pull PD.3 to Low and check PD.4 status */
GPIO_ClrBit(GPIOD, BIT3);
if(GPIO_ReadBit(GPIOD,BIT4)==1)
i32Err = 1;
if(i32Err)
{
sysprintf(" [FAIL].\n");
}
else
{
sysprintf(" [OK].\n");
}
/* Configure PD3 to default value */
GPIO_CloseBit(GPIOD, BIT3);
/* Configure PD4 to default value */
GPIO_CloseBit(GPIOD, BIT3);
/* Set MFP_GPF11 to EINT0 */
outpw(REG_SYS_GPF_MFPH,(inpw(REG_SYS_GPF_MFPH) & ~(0xF<<12)) | (0xF<<12));
/* Configure PF11 to input mode and pull-up */
GPIO_OpenBit(GPIOF, BIT11, DIR_INPUT, PULL_UP);
/* Confingure PF11 to rising-edge trigger */
GPIO_EnableTriggerType(GPIOF, BIT11,RISING);
/* Enable external 0 interrupt */
GPIO_EnableEINT(NIRQ0, (GPIO_CALLBACK)EINT0Callback, 0);
/* waiting for external 0 interrupt */
sysprintf("waiting for PF11 rsing-edge trigger...");
while(!eint_complete);
/* Disable PF11 trigger type */
GPIO_DisableTriggerType(GPIOF, BIT11);
/* Enable external 0 interrupt */
GPIO_DisableEINT(NIRQ0);
sysprintf(" [OK].\n");
/* Configure PF11 to default value */
GPIO_CloseBit(GPIOF, BIT11);
/* Configure PE3 to output mode */
GPIO_OpenBit(GPIOE, BIT3, DIR_INPUT, NO_PULL_UP);
/* Confingure PE3 to falling-edge trigger */
GPIO_EnableTriggerType(GPIOE, BIT3,FALLING);
/* Enable GPIOE interrupt */
GPIO_EnableInt(GPIOE, (GPIO_CALLBACK)GPIOECallback, 0);
/* waiting for external 0 interrupt */
sysprintf("waiting for PE3 falling-edge trigger...");
while(!gpio_complete);
/* Disable PE3 to trigger type */
GPIO_DisableTriggerType(GPIOE, BIT3);
/* Disable GPIOE interrupt */
GPIO_DisableInt(GPIOE);
/* Configure PE0 to default value */
GPIO_CloseBit(GPIOE, BIT3);
sysprintf(" [OK].\n");
while(1);
}
int32_t main(void)
{
uint8_t *u8FrameBufPtr, *u8OSDFrameBufPtr, i;
outpw(REG_CLK_HCLKEN, 0x0527);
outpw(REG_CLK_PCLKEN0, 0);
outpw(REG_CLK_PCLKEN1, 0);
sysDisableCache();
sysFlushCache(I_D_CACHE);
sysEnableCache(CACHE_WRITE_BACK);
sysInitializeUART();
// Configure multi-function pin for LCD interface
//GPG6 (CLK), GPG7 (HSYNC)
outpw(REG_SYS_GPG_MFPL, (inpw(REG_SYS_GPG_MFPL)& ~0xFF000000) | 0x22000000);
//GPG8 (VSYNC), GPG9 (DEN)
outpw(REG_SYS_GPG_MFPH, (inpw(REG_SYS_GPG_MFPH)& ~0xFF) | 0x22);
//DATA pin
//GPA0 ~ GPA7 (DATA0~7)
outpw(REG_SYS_GPA_MFPL, 0x22222222);
//GPA8 ~ GPA15 (DATA8~15)
outpw(REG_SYS_GPA_MFPH, 0x22222222);
//GPD8~D15 (DATA16~23)
outpw(REG_SYS_GPD_MFPH, (inpw(REG_SYS_GPD_MFPH)& ~0xFFFFFFFF) | 0x22222222);
// LCD clock is selected from UPLL and divide to 20MHz
outpw(REG_CLK_DIVCTL1, (inpw(REG_CLK_DIVCTL1) & ~0xff1f) | 0xe18);
// Init LCD interface for E50A2V1 LCD module
vpostLCMInit(DIS_PANEL_E50A2V1);
// Set scale to 1:1
vpostVAScalingCtrl(1, 0, 1, 0, VA_SCALE_INTERPOLATION);
// Set display color depth
#ifdef DISPLAY_RGB888
vpostSetVASrc(VA_SRC_RGB888);
#else
vpostSetVASrc(VA_SRC_RGB565);
#endif
// Get pointer of video frame buffer
// Note: before get pointer of frame buffer, must set display color depth first
u8FrameBufPtr = vpostGetFrameBuffer();
if(u8FrameBufPtr == NULL)
{
sysprintf("Get buffer error !!\n");
return 0;
}
// Set OSD position and display size
vpostOSDSetWindow(240, 120, 320, 240);
// Set OSD color depth
#ifdef DISPLAY_RGB888
vpostSetOSDSrc(OSD_SRC_RGB888);
#else
vpostSetOSDSrc(OSD_SRC_RGB565);
#endif
// Get pointer of OSD frame buffer
// Note: before get pointer of frame buffer, must set display size and display color depth first
u8OSDFrameBufPtr = vpostGetOSDBuffer();
if(u8OSDFrameBufPtr == NULL)
{
sysprintf("Get OSD buffer error !!\n");
return 0;
}
// Set scale to 1:1
vpostOSDScalingCtrl(1, 0, 0);
// Configure overlay function of OSD to display OSD image
vpostOSDSetOverlay(DISPLAY_OSD, DISPLAY_OSD, 0);
// Enable color key function
vpostOSDSetColKey(0, 0, 0);
// Prepare image
#ifdef DISPLAY_RGB888
memcpy((void *)u8FrameBufPtr, (void *)&video_img[0], 800*480*4);
memcpy((void *)u8OSDFrameBufPtr, (void *)&osd_img[0], 320*240*4);
#else
memcpy((void *)u8FrameBufPtr, (void *)&video_img[0], 800*480*2);
memcpy((void *)u8OSDFrameBufPtr, (void *)&osd_img[0], 320*240*2);
#endif
// Prepare hardware cursor image (color bar)
for (i=0;i<16;i++)
{
u32CursorBuf[i] = 0x00;
u32CursorBuf[i+16*1] = 0x55555555;
u32CursorBuf[i+16*2] = 0xaaaaaaaa;
u32CursorBuf[i+16*3] = 0xffffffff;
u32CursorBuf[i+16*4] = 0x00;
u32CursorBuf[i+16*5] = 0x55555555;
u32CursorBuf[i+16*6] = 0xaaaaaaaa;
u32CursorBuf[i+16*7] = 0xffffffff;
u32CursorBuf[i+16*8] = 0x00;
u32CursorBuf[i+16*9] = 0x55555555;
u32CursorBuf[i+16*10] = 0xaaaaaaaa;
u32CursorBuf[i+16*11] = 0xffffffff;
u32CursorBuf[i+16*12] = 0x00;
u32CursorBuf[i+16*13] = 0x55555555;
u32CursorBuf[i+16*14] = 0xaaaaaaaa;
u32CursorBuf[i+16*15] = 0xffffffff;
u32CursorBuf[i+16*16] = 0x00;
u32CursorBuf[i+16*17] = 0x55555555;
u32CursorBuf[i+16*18] = 0xaaaaaaaa;
u32CursorBuf[i+16*19] = 0xffffffff;
u32CursorBuf[i+16*20] = 0x00;
u32CursorBuf[i+16*21] = 0x55555555;
u32CursorBuf[i+16*22] = 0xaaaaaaaa;
u32CursorBuf[i+16*23] = 0xffffffff;
u32CursorBuf[i+16*24] = 0x00;
u32CursorBuf[i+16*25] = 0x55555555;
u32CursorBuf[i+16*26] = 0xaaaaaaaa;
u32CursorBuf[i+16*27] = 0xffffffff;
u32CursorBuf[i+16*28] = 0x00;
u32CursorBuf[i+16*29] = 0x55555555;
u32CursorBuf[i+16*30] = 0xaaaaaaaa;
u32CursorBuf[i+16*31] = 0xffffffff;
}
// Start video and OSD
vpostVAStartTrigger();
vpostOSDEnable();
// Start hardware cursor
vpostHCInit(u32CursorBuf, HC_MODE0);
// Set hardware cursor position
vpostHCPosCtrl(50, 50);
while(1);
}
int32_t main(void)
{
uint16_t u16ID;
uint32_t u32ByteCount, u32FlashAddress, u32PageNumber;
uint32_t nError = 0;
outpw(REG_CLK_HCLKEN, 0x0527);
outpw(REG_CLK_PCLKEN0, 0);
outpw(REG_CLK_PCLKEN1, 0);
sysDisableCache();
sysFlushCache(I_D_CACHE);
sysEnableCache(CACHE_WRITE_BACK);
sysInitializeUART();
/* Configure multi function pins to SPI0 */
outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & ~0xff000000) | 0xBB000000);
outpw(REG_SYS_GPB_MFPH, (inpw(REG_SYS_GPB_MFPH) & ~0xff) | 0xBB);
spiInit(0);
spiOpen(0);
// set spi interface speed to 2MHz
spiIoctl(0, SPI_IOC_SET_SPEED, 2000000, 0);
// set transfer length to 8-bit
spiIoctl(0, SPI_IOC_SET_TX_BITLEN, 8, 0);
// set transfer mode to mode-0
spiIoctl(0, SPI_IOC_SET_MODE, 0, 0);
// check flash id
if((u16ID = SpiFlash_ReadMidDid()) == 0xEF17) {
sysprintf("Flash found: W25Q128BV ...\n");
} else
sysprintf("Flash ID, 0x%x\n", u16ID);
sysprintf("Erase chip ...");
/* Erase SPI flash */
SpiFlash_ChipErase();
/* Wait ready */
SpiFlash_WaitReady();
sysprintf("[OK]\n");
/* init source data buffer */
for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
SrcArray[u32ByteCount] = u32ByteCount;
}
sysprintf("Start to normal write data to Flash ...");
/* Program SPI flash */
u32FlashAddress = 0;
for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
/* page program */
SpiFlash_NormalPageProgram(u32FlashAddress, SrcArray);
SpiFlash_WaitReady();
u32FlashAddress += 0x100;
}
sysprintf("[OK]\n");
/* clear destination data buffer */
for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
DestArray[u32ByteCount] = 0;
}
sysprintf("Normal Read & Compare ...");
/* Read SPI flash */
u32FlashAddress = 0;
for(u32PageNumber=0; u32PageNumber<TEST_NUMBER; u32PageNumber++) {
/* page read */
SpiFlash_NormalRead(u32FlashAddress, DestArray);
u32FlashAddress += 0x100;
for(u32ByteCount=0; u32ByteCount<TEST_LENGTH; u32ByteCount++) {
if(DestArray[u32ByteCount] != SrcArray[u32ByteCount])
nError ++;
}
}
if(nError == 0)
sysprintf("[OK]\n");
else
sysprintf("[FAIL]\n");
return 1;
}