/* Boot PROM (OpenBIOS) */ static void prom_init(hwaddr addr, const char *bios_name) { DeviceState *dev; SysBusDevice *s; char *filename; int ret; dev = qdev_create(NULL, "openprom"); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, addr); /* load boot prom */ if (bios_name == NULL) { bios_name = PROM_FILENAME; } filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { ret = load_elf(filename, translate_prom_address, &addr, NULL, NULL, NULL, 1, ELF_MACHINE, 0); if (ret < 0 || ret > PROM_SIZE_MAX) { ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); } g_free(filename); } else { ret = -1; } if (ret < 0 || ret > PROM_SIZE_MAX) { fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); exit(1); } }
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port, target_phys_addr_t ctl_addr, target_phys_addr_t data_addr) { DeviceState *dev; SysBusDevice *d; FWCfgState *s; dev = qdev_create(NULL, "fw_cfg"); qdev_prop_set_uint32(dev, "ctl_iobase", ctl_port); qdev_prop_set_uint32(dev, "data_iobase", data_port); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); s = DO_UPCAST(FWCfgState, busdev.qdev, dev); if (ctl_addr) { sysbus_mmio_map(d, 0, ctl_addr); } if (data_addr) { sysbus_mmio_map(d, 1, data_addr); } fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4); fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16); fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC)); fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu); s->machine_ready.notify = fw_cfg_machine_ready; qemu_add_machine_init_done_notifier(&s->machine_ready); return s; }
/* Legacy helper function. */ void arm_sysctl_init(uint32_t base, uint32_t sys_id) { DeviceState *dev; dev = qdev_create(NULL, "realview_sysctl"); qdev_prop_set_uint32(dev, "sys_id", sys_id); qdev_init(dev); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); }
DeviceState *s5pc1xx_onedram_init(const char *name, target_phys_addr_t base, qemu_irq irq_ap) { DeviceState *dev = qdev_create(NULL, name); ram_addr_t onedram_shared, onedram_ap; qdev_init_nofail(dev); onedram_ap = qemu_ram_alloc(ONEDRAM_AP_SIZE); cpu_register_physical_memory(base, ONEDRAM_AP_SIZE, onedram_ap | IO_MEM_RAM); onedram_shared = qemu_ram_alloc(ONEDRAM_SHARED_SIZE); cpu_register_physical_memory(base + ONEDRAM_AP_SIZE, ONEDRAM_SHARED_SIZE, onedram_shared | IO_MEM_RAM); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base + ONEDRAM_AP_SIZE + ONEDRAM_SFR); sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq_ap); return dev; }
void pc_basic_device_init(qemu_irq *isa_irq, FDCtrl **floppy_controller, ISADevice **rtc_state) { int i; DriveInfo *fd[MAX_FD]; PITState *pit; qemu_irq rtc_irq = NULL; qemu_irq *a20_line; ISADevice *i8042; qemu_irq *cpu_exit_irq; register_ioport_write(0x80, 1, 1, ioport80_write, NULL); register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); if (!no_hpet) { DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL); for (i = 0; i < 24; i++) { sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]); } rtc_irq = qdev_get_gpio_in(hpet, 0); } *rtc_state = rtc_init(2000, rtc_irq); qemu_register_boot_set(pc_boot_set, *rtc_state); pit = pit_init(0x40, isa_reserve_irq(0)); pcspk_init(pit); for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { serial_isa_init(i, serial_hds[i]); } } for(i = 0; i < MAX_PARALLEL_PORTS; i++) { if (parallel_hds[i]) { parallel_init(i, parallel_hds[i]); } } a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1); i8042 = isa_create_simple("i8042"); i8042_setup_a20_line(i8042, a20_line); vmmouse_init(i8042); cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); DMA_init(0, cpu_exit_irq); for(i = 0; i < MAX_FD; i++) { fd[i] = drive_get(IF_FLOPPY, 0, i); } *floppy_controller = fdctrl_init_isa(fd); }
static void lan9118_reset(DeviceState *d) { lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); s->irq_cfg &= (IRQ_TYPE | IRQ_POL); s->int_sts = 0; s->int_en = 0; s->fifo_int = 0x48000000; s->rx_cfg = 0; s->tx_cfg = 0; s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004; s->pmt_ctrl &= 0x45; s->gpio_cfg = 0; s->txp->fifo_used = 0; s->txp->state = TX_IDLE; s->txp->cmd_a = 0xffffffffu; s->txp->cmd_b = 0xffffffffu; s->txp->len = 0; s->txp->fifo_used = 0; s->tx_fifo_size = 4608; s->tx_status_fifo_used = 0; s->rx_status_fifo_size = 704; s->rx_fifo_size = 2640; s->rx_fifo_used = 0; s->rx_status_fifo_size = 176; s->rx_status_fifo_used = 0; s->rxp_offset = 0; s->rxp_size = 0; s->rxp_pad = 0; s->rx_packet_size_tail = s->rx_packet_size_head; s->rx_packet_size[s->rx_packet_size_head] = 0; s->mac_cmd = 0; s->mac_data = 0; s->afc_cfg = 0; s->e2p_cmd = 0; s->e2p_data = 0; s->free_timer_start = qemu_get_clock_ns(vm_clock) / 40; ptimer_stop(s->timer); ptimer_set_count(s->timer, 0xffff); s->gpt_cfg = 0xffff; s->mac_cr = MAC_CR_PRMS; s->mac_hashh = 0; s->mac_hashl = 0; s->mac_mii_acc = 0; s->mac_mii_data = 0; s->mac_flow = 0; s->read_word_n = 0; s->write_word_n = 0; phy_reset(s); s->eeprom_writable = 0; lan9118_reload_eeprom(s); }
static void highbank_regs_reset(DeviceState *dev) { SysBusDevice *sys_dev = sysbus_from_qdev(dev); HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev); s->regs[0x40] = 0x05F20121; s->regs[0x41] = 0x2; s->regs[0x42] = 0x05F30121; s->regs[0x43] = 0x05F40121; }
void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) { SysBusDevice *s = sysbus_from_qdev(dev); int i; for (i = 0; i < s->num_mmio; i++) { monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", indent, "", s->mmio[i].addr, s->mmio[i].size); } }
static void nand_reset(DeviceState *dev) { NANDFlashState *s = FROM_SYSBUS(NANDFlashState, sysbus_from_qdev(dev)); s->cmd = NAND_CMD_READ0; s->addr = 0; s->addrlen = 0; s->iolen = 0; s->offset = 0; s->status &= NAND_IOSTATUS_UNPROTCT; }
static int exynos4210_gic_init(SysBusDevice *dev) { Exynos4210GicState *s = FROM_SYSBUS(Exynos4210GicState, dev); uint32_t i; const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; const char dist_prefix[] = "exynos4210-gic-alias_dist"; char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; SysBusDevice *busdev; s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); qdev_init_nofail(s->gic); busdev = sysbus_from_qdev(s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(&s->busdev.qdev, exynos4210_gic_set_irq, EXYNOS4210_GIC_NIRQ - 32); memory_region_init(&s->cpu_container, "exynos4210-cpu-container", EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); memory_region_init(&s->dist_container, "exynos4210-dist-container", EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); for (i = 0; i < s->num_cpu; i++) { /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], cpu_alias_name, sysbus_mmio_get_region(busdev, 1), 0, EXYNOS4210_GIC_CPU_REGION_SIZE); memory_region_add_subregion(&s->cpu_container, EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); /* Map Distributor per SMP Core */ sprintf(dist_alias_name, "%s%x", dist_prefix, i); memory_region_init_alias(&s->dist_alias[i], dist_alias_name, sysbus_mmio_get_region(busdev, 0), 0, EXYNOS4210_GIC_DIST_REGION_SIZE); memory_region_add_subregion(&s->dist_container, EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); } sysbus_init_mmio(dev, &s->cpu_container); sysbus_init_mmio(dev, &s->dist_container); return 0; }
static void arm_sysctl_reset(DeviceState *d) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d)); s->leds = 0; s->lockval = 0; s->cfgdata1 = 0; s->cfgdata2 = 0; s->flags = 0; s->resetlevel = 0; }
static void arm_mptimer_reset(DeviceState *dev) { arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev)); int i; /* We reset every timer in the array, not just the ones we're using, * because vmsave will look at every array element. */ for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { timerblock_reset(&s->timerblock[i]); } }
static void iphone2g_radio_init() { DeviceState *dev = qdev_create(NULL, "s5l8900.uart"); char str[] = "s5l8900.uart.00"; S5L8900UartState *s = FROM_SYSBUS(S5L8900UartState, dev); s->base = base; if (!chr) { fprintf(stderr, "openning char device"); snprintf(str, strlen(str) + 1, "s5l8900.uart.%02d", instance % 100); chr = qemu_chr_open(str, "null", NULL); } qdev_prop_set_chr(dev, "chr", chr); qdev_prop_set_uint32(dev, "queue-size", queue_size); qdev_prop_set_uint32(dev, "instance", instance); qdev_init_nofail(dev); sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); return dev; }
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) { SysBusDevice *s = sysbus_from_qdev(dev); hwaddr size; int i; monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq); for (i = 0; i < s->num_mmio; i++) { size = memory_region_size(s->mmio[i].memory); monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", indent, "", s->mmio[i].addr, size); } }
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "cadence_gem"); dev = qdev_create(NULL, "cadence_gem"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }
/* Legacy helper function. Should go away when machine config files are implemented. */ void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; qemu_check_nic_model(nd, "smc91c111"); dev = qdev_create(NULL, "smc91c111"); qdev_set_netdev(dev, nd); qdev_init(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); }
static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "mipsnet"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_connect_irq(s, 0, irq); memory_region_add_subregion(get_system_io(), base, sysbus_mmio_get_region(s, 0)); }
static void ioapic_init(IsaIrqState *isa_irq_state) { DeviceState *dev; SysBusDevice *d; unsigned int i; dev = qdev_create(NULL, "ioapic"); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i); } }
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) { DeviceState *dev; SysBusDevice *s; RamDevice *d; /* allocate RAM */ dev = qdev_create(NULL, "memory"); s = sysbus_from_qdev(dev); d = FROM_SYSBUS(RamDevice, s); d->size = RAM_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); }
static void lan9215_init(uint32_t base, qemu_irq irq) { DeviceState *dev; SysBusDevice *s; /* This should be a 9215 but the 9118 is close enough */ if (nd_table[0].used) { qemu_check_nic_model(&nd_table[0], "lan9118"); dev = qdev_create(NULL, "lan9118"); qdev_set_nic_properties(dev, &nd_table[0]); qdev_prop_set_uint32(dev, "mode_16bit", 1); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_mmio_map(s, 0, base); sysbus_connect_irq(s, 0, irq); } }
static char *sysbus_get_fw_dev_path(DeviceState *dev) { SysBusDevice *s = sysbus_from_qdev(dev); char path[40]; int off; off = snprintf(path, sizeof(path), "%s", qdev_fw_name(dev)); if (s->num_mmio) { snprintf(path + off, sizeof(path) - off, "@"TARGET_FMT_plx, s->mmio[0].addr); } else if (s->num_pio) { snprintf(path + off, sizeof(path) - off, "@i%04x", s->pio[0]); } return g_strdup(path); }
static void arm_sysctl_reset(DeviceState *d) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d)); s->leds = 0; s->lockval = 0; s->cfgdata1 = 0; s->cfgdata2 = 0; s->flags = 0; s->resetlevel = 0; if (board_id(s) == BOARD_ID_VEXPRESS) { /* On VExpress this register will RAZ/WI */ s->sys_clcd = 0; } else { /* All others: CLCDID 0x1f, indicating VGA */ s->sys_clcd = 0x1f00; } }
void empty_slot_init(hwaddr addr, uint64_t slot_size) { if (slot_size > 0) { /* Only empty slots larger than 0 byte need handling. */ DeviceState *dev; SysBusDevice *s; EmptySlot *e; dev = qdev_create(NULL, "empty_slot"); s = sysbus_from_qdev(dev); e = FROM_SYSBUS(EmptySlot, s); e->size = slot_size; qdev_init_nofail(dev); sysbus_mmio_map(s, 0, addr); } }
static void ioapic_init(GSIState *gsi_state) { DeviceState *dev; SysBusDevice *d; unsigned int i; if (kvm_enabled() && kvm_irqchip_in_kernel()) { dev = qdev_create(NULL, "kvm-ioapic"); } else { dev = qdev_create(NULL, "ioapic"); } qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); } }
static void openrisc_sim_net_init(MemoryRegion *address_space, hwaddr base, hwaddr descriptors, qemu_irq irq, NICInfo *nd) { DeviceState *dev; SysBusDevice *s; dev = qdev_create(NULL, "open_eth"); qdev_set_nic_properties(dev, nd); qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_connect_irq(s, 0, irq); memory_region_add_subregion(address_space, base, sysbus_mmio_get_region(s, 0)); memory_region_add_subregion(address_space, descriptors, sysbus_mmio_get_region(s, 1)); }
static void smc91c111_reset(DeviceState *dev) { smc91c111_state *s = FROM_SYSBUS(smc91c111_state, sysbus_from_qdev(dev)); s->bank = 0; s->tx_fifo_len = 0; s->tx_fifo_done_len = 0; s->rx_fifo_len = 0; s->allocated = 0; s->packet_num = 0; s->tx_alloc = 0; s->tcr = 0; s->rcr = 0; s->cr = 0xa0b1; s->ctr = 0x1210; s->ptr = 0; s->ercv = 0x1f; s->int_level = INT_TX_EMPTY; s->int_mask = 0; smc91c111_update(s); }
static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, bool is_qspi) { DeviceState *dev; SysBusDevice *busdev; SSIBus *spi; DeviceState *flash_dev; int i, j; int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; dev = qdev_create(NULL, "xilinx,spips"); qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); qdev_prop_set_uint8(dev, "num-busses", num_busses); qdev_init_nofail(dev); busdev = sysbus_from_qdev(dev); sysbus_mmio_map(busdev, 0, base_addr); if (is_qspi) { sysbus_mmio_map(busdev, 1, 0xFC000000); } sysbus_connect_irq(busdev, 0, irq); for (i = 0; i < num_busses; ++i) { char bus_name[16]; qemu_irq cs_line; snprintf(bus_name, 16, "spi%d", i); spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); for (j = 0; j < num_ss; ++j) { flash_dev = ssi_create_slave_no_init(spi, "m25p80"); qdev_prop_set_string(flash_dev, "partname", "n25q128"); qdev_init_nofail(flash_dev); cs_line = qdev_get_gpio_in(flash_dev, 0); sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); } } }
void esp_init(target_phys_addr_t espaddr, int it_shift, ESPDMAMemoryReadWriteFunc dma_memory_read, ESPDMAMemoryReadWriteFunc dma_memory_write, void *dma_opaque, qemu_irq irq, qemu_irq *reset) { DeviceState *dev; SysBusDevice *s; ESPState *esp; dev = qdev_create(NULL, "esp"); esp = DO_UPCAST(ESPState, busdev.qdev, dev); esp->dma_memory_read = dma_memory_read; esp->dma_memory_write = dma_memory_write; esp->dma_opaque = dma_opaque; esp->it_shift = it_shift; qdev_init_nofail(dev); s = sysbus_from_qdev(dev); sysbus_connect_irq(s, 0, irq); sysbus_mmio_map(s, 0, espaddr); *reset = qdev_get_gpio_in(dev, 0); }
static void ioapic_init(GSIState *gsi_state) { DeviceState *dev; SysBusDevice *d; unsigned int i; if (kvm_irqchip_in_kernel()) { dev = qdev_create(NULL, "kvm-ioapic"); } else { dev = qdev_create(NULL, "ioapic"); } /* FIXME: this should be under the piix3. */ object_property_add_child(object_resolve_path("i440fx", NULL), "ioapic", OBJECT(dev), NULL); qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); for (i = 0; i < IOAPIC_NUM_PINS; i++) { gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); } }
static void arm_gic_common_reset(DeviceState *dev) { gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev)); int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { s->priority_mask[i] = 0xf0; s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; s->cpu_enabled[i] = 0; } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_TRIGGER(i); } if (s->num_cpu == 1) { /* For uniprocessor GICs all interrupts always target the sole CPU */ for (i = 0; i < GIC_MAXIRQ; i++) { s->irq_target[i] = 1; } } s->enabled = 0; }