static void stih415_ethernet_gmii_speed(int port, void *priv,
unsigned int speed)
{
/* TX Clock inversion is not set for 1000Mbps */
if (speed == SPEED_1000)
sysconf_write(gbit_sc[port], 0);
else
sysconf_write(gbit_sc[port], 1);
stih415_ethernet_gtx_speed(priv, speed);
}
static void stx7108_pcie_init(void *handle)
{
struct sysconf_field *sc = (struct sysconf_field *) handle;
/* Drive RST_N low, set device type */
sysconf_write(sc, PCIE_DEVICE_TYPE);
sysconf_write(sc, PCIE_DEFAULT_VAL);
mdelay(1);
}
static void snd_stm_stih415_setup(void)
{
/* Select external pcm clock for each channel */
sysconf_write(snd_stm_stih415_pcm_clk_sel, 0xf);
/* Set bi-phase idle value */
sysconf_write(snd_stm_stih415_biphase_idle_value, 0);
/* Clear all voip bits for now */
sysconf_write(snd_stm_stih415_voip, 0);
/* Route pcm players */
sysconf_write(snd_stm_stih415_pcmp_valid_sel, 1);
}
static int stm_miphy_tap_tick(int tms, int tdi)
{
sysconf_write(tap_dev->tck, 0);
sysconf_write(tap_dev->tms, tms);
sysconf_write(tap_dev->tdi, tdi);
sysconf_write(tap_dev->tck, 1);
return sysconf_read(tap_dev->tdo);
}
static void stih415_restart_sata(int port)
{
/* This part of the code is executed for ESD recovery.*/
/* Reset the SATA Host and MiPHY */
sysconf_write(sc_sata_hc_pwr[port], 1);
sysconf_write(sc_miphy_reset[port], 0);
if (port == 1)
stih415_pcie_mp_select(1);
msleep(1);
sysconf_write(sc_sata_hc_pwr[port], 0);
sysconf_write(sc_miphy_reset[port], 1);
}
static int
usb_sw_reset(struct platform_device *dev, int host_phy)
{
static struct sysconf_field *sc;
/* Reset USB */
if (!sc)
sc = sysconf_claim(SYS_CFG, 4, 4, 4, "USB_RST");
sysconf_write(sc, 0);
mdelay(10);
sysconf_write(sc, 1);
mdelay(10);
return 0;
}
int __init device_init_stb840_promSvyaz(int ver)
{
struct sysconf_field *sc;
stx7105_configure_sata(0);
/* Set SPI Boot pads as inputs to avoid contention with SSC1 */
gpio_request(stm_gpio(15, 0), "SPI Boot CLK");
gpio_direction_input(stm_gpio(15, 0));
gpio_request(stm_gpio(15, 1), "SPI Boot DOUT");
gpio_direction_input(stm_gpio(15, 1));
gpio_request(stm_gpio(15, 2), "SPI Boot NOTCS");
gpio_direction_input(stm_gpio(15, 2));
gpio_request(stm_gpio(15, 3), "SPI Boot DIN");
gpio_direction_input(stm_gpio(15, 3));
/*
* Fix the reset chain so it correct to start with in case the
* watchdog expires or we trigger a reset.
*/
sc = sysconf_claim(SYS_CFG, 9, 27, 28, "reset_chain");
sysconf_write(sc, 0);
/* Release the sysconf bits so the coprocessor driver can claim them */
sysconf_release(sc);
/* I2C_xxxA - HDMI */
stx7105_configure_ssc_i2c(0, &(struct stx7105_ssc_config) {
.routing.ssc0.sclk = stx7105_ssc0_sclk_pio2_2,
.routing.ssc0.mtsr = stx7105_ssc0_mtsr_pio2_3, });
static int
usb_pwr_dwn(struct platform_device *dev, int host_phy, int pwd)
{
static struct sysconf_field *sc, *sc_clk;
/* Power on USB */
if (!sc) {
sc = sysconf_claim(SYS_CFG, 32, 4, 4, "USB_PW_REQ");
sc_clk = sysconf_claim(SYS_CFG, 40, 2, 3, "usb_clk");
}
sysconf_write(sc, (pwd ? 1 : 0));
sysconf_write(sc_clk, (pwd ? 3 : 0));
return 0;
}
int __init stmcore_probe_device(struct stmcore_display_pipeline_data **pd, int *nr_platform_devices)
{
if(boot_cpu_data.type == CPU_STX7106)
{
*pd = platform_data;
*nr_platform_devices = N_ELEMENTS (platform_data);
/*
* Setup HDMI hotplug
*/
hotplug_pio = stpio_request_pin(9,7,"HDMI Hotplug",STPIO_IN);
if (hotplug_pio)
{
/* enable hotplug pio in syscfg */
syscfg2_27 = sysconf_claim (SYS_CFG, 2, 27, 27, "HDMI Hotplug PIO enable");
sysconf_write (syscfg2_27, 1);
printk (KERN_INFO "stmcore-display: using HDMI hotplug\n");
}
else
printk (KERN_INFO "stmcore-display: HDMI hotplug not available\n");
printk(KERN_WARNING "stmcore-display: STi7106 display: probed\n");
return 0;
}
printk(KERN_WARNING "stmcore-display: STi7106 display: platform unknown\n");
return -ENODEV;
}
int __init stmcore_probe_device(struct stmcore_display_pipeline_data **pd, int *nr_platform_devices)
{
if(boot_cpu_data.type == CPU_STX7141)
{
unsigned long syscfg20;
*pd = platform_data;
*nr_platform_devices = N_ELEMENTS (platform_data);
/*
* Setup HDMI hotplug
*/
hotplug_pio = stpio_request_pin(5,6,"HDMI Hotplug",STPIO_IN);
/*
* Enable hotplug pio in syscfg
*/
syscfg20_24 = sysconf_claim(SYS_CFG,20,24,24,"HDMI Hotplug PIO ALT Function");
sysconf_write(syscfg20_24,1);
printk(KERN_WARNING "stmcore-display: STi7141 display probed\n");
return 0;
}
printk(KERN_WARNING "stmcore-display: STi7141 display not found\n");
return -ENODEV;
}
static void stx7108_ethernet_rmii_speed(void *priv, unsigned int speed)
{
struct stx7108_stmmac_priv *stmmac_priv = priv;
struct sysconf_field *mac_speed_sel = stmmac_priv->mac_speed_sel;
sysconf_write(mac_speed_sel, (speed == SPEED_100) ? 1 : 0);
}
static void stxh205_pcie_init(void *handle)
{
struct sysconf_field *sc = (struct sysconf_field *) handle;
sysconf_write(sc, PCIE_DEFAULT_VAL);
mdelay(1);
}
static int __init stx7108_configure_miphy_uport(void)
{
struct sysconf_field *sc_miphy1_ref_clk,
*sc_sata1_hc_reset, *sc_sata_pcie_sel,
*sc_sata1_hc_srst;
sc_pcie_mp_select = sysconf_claim(SYS_CFG_BANK4, 70,
0, 0, "pcie-mp");
BUG_ON(!sc_pcie_mp_select);
/* SATA0_SOFT_RST_N_SATA: sata0_soft_rst_n_sata. */
/* Useless documentation R us */
sc_sata1_hc_srst = sysconf_claim(SYS_CFG_BANK4, 45, 4, 4, "MiPHY");
BUG_ON(!sc_sata1_hc_srst);
/* SELECT_SATA: select_sata. */
sc_sata_pcie_sel = sysconf_claim(SYS_CFG_BANK4, 68, 1, 1, "MiPHY");
BUG_ON(!sc_sata_pcie_sel);
/* SATAPHY1_OSC_FORCE_EXT: SATAphy1_osc_force_ext. */
sc_miphy1_ref_clk = sysconf_claim(SYS_CFG_BANK4, 68, 2, 2, "MiPHY");
BUG_ON(!sc_miphy1_ref_clk);
/* RESETGEN_CONF0_1: Active low Software Reset for peripherals <31:0>.
* NOTE documenation appears to be wrong!
* RST_PER_N_30: SATA_2XHOST */
sc_sata1_hc_reset = sysconf_claim(SYS_CFG_BANK0,
BANK0_REG(12), 30, 30, "SATA");
BUG_ON(!sc_sata1_hc_reset);
/* Deassert Soft Reset to SATA0 */
sysconf_write(sc_sata1_hc_srst, 1);
/* If the 100MHz xtal for PCIe is present, then the microport interface
* will already have a clock, so there is no need to flip to the 30MHz
* clock here. If it isn't then we have to switch miphy lane 1 to use
* the 30MHz clock, as otherwise we will not be able to talk to lane 0
* since the uport interface itself is clocked from lane1
*/
if (stx7108_miphy_modes[1] != PCIE_MODE) {
/* Put MiPHY1 in reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 0);
/* Put SATA1 HC in reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 0);
/* Now switch to Phy interface to SATA HC not PCIe HC */
sysconf_write(sc_sata_pcie_sel, 1);
/* Select the Uport to use MiPHY1 */
stx7108_pcie_mp_select(1);
/* Take SATA1 HC out of reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 1);
/* MiPHY1 needs to be using the MiPHY0 reference clock */
sysconf_write(sc_miphy1_ref_clk, 1);
/* Take MiPHY1 out of reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 1);
}
stx7108_using_uport = 1;
return platform_device_register(&stx7108_pcie_mp_device);
}
void stm_device_sysconf_write(struct stm_device_state *state,
const char* name, unsigned long long value)
{
int i;
i = stm_device_find_sysconf(state->config, name);
WARN_ON(i < 0);
if (i >= 0)
sysconf_write(state->sysconf_fields[i], value);
}
static void stih415_ethernet_rgmii_speed(int port, void *priv,
unsigned int speed)
{
/* TX Clock inversion is not set for 1000Mbps */
if (speed == SPEED_1000) {
/* output clock driver by MII_TXCLK
* 125Mhz Clock from PHY is used for retiming
* and also to drive GTXCLK
* */
sysconf_write(gbit_sc[port], 0);
} else {
int ret;
static struct clk *phy_clk, *clk_parent;
unsigned long phy_clk_rate;
/* output clock driver by Clockgen
* 125MHz clock provided by PHY is not suitable for retiming.
* So TXPIO retiming must therefore be clocked by an
* internal 2.5/25Mhz clock generated by Clockgen.
* */
phy_clk = clk_get(NULL, gmac_clk_n[port]);
sysconf_write(gbit_sc[port], 6);
if (speed == SPEED_100) {
clk_parent = clk_get(NULL, phy_clk_parent_100[port]);
phy_clk_rate = 25000000;
} else {
/*
* We have to route the phy clk to a parent
* (e.g. 30MHz quartz) to get 2.5MHz for RGMII.
*/
clk_parent = clk_get(NULL, phy_clk_parent_10[port]);
phy_clk_rate = 2500000;
}
ret = clk_set_parent(phy_clk, clk_parent);
if (ret)
pr_err("%s: error setting the parent clk\n", __func__);
clk_set_rate(phy_clk, phy_clk_rate);
pr_debug("%s: %d Speed - phy clk %lu\n", __func__,
speed, clk_get_rate(phy_clk));
}
stih415_ethernet_gtx_speed(priv, speed);
}
static int
emi_pwr_dwn_req(struct platform_device *dev, int host_phy, int dwn)
{
static struct sysconf_field *sc;
if (!sc)
sc = sysconf_claim(SYS_CFG, 32, 1, 1, "emi pwr");
sysconf_write(sc, (dwn ? 1 : 0));
return 0;
}
int stih415_gmac1_claim(struct stm_pad_state *state, void *priv)
{
gbit_sc[1] = sysconf_claim(SYSCONF(29), 6, 8, "gmac-1");
if (!gbit_sc[1])
return -1;
sysconf_write(gbit_sc[1], 0);
return 0;
}
int stih415_gmac0_claim(struct stm_pad_state *state, void *priv)
{
gbit_sc[0] = sysconf_claim(SYSCONF(382), 6, 8, "gmac-0");
if (!gbit_sc[0])
return -1;
sysconf_write(gbit_sc[0], 0);
return 0;
}
static int
usb_pm_pwd_dwn(struct platform_device *dev, int host_phy, int pwd)
{
static struct sysconf_field *sc;
if(!sc)
sc = sysconf_claim(SYS_CFG, 2, 4, 5, "usb rx/tx");
sysconf_write(sc, (pwd ? 0 : 3));
return 0;
}
static int snd_stm_conv_dac_sc_set_muted(int muted, void *priv)
{
struct snd_stm_conv_dac_sc *conv_dac_sc = priv;
snd_stm_printd(1, "snd_stm_conv_dac_sc_set_muted(muted=%d, priv=%p)\n",
muted, priv);
BUG_ON(!conv_dac_sc);
BUG_ON(!snd_stm_magic_valid(conv_dac_sc));
snd_stm_printd(1, "%suting DAC %s.\n", muted ? "M" : "Unm",
conv_dac_sc->bus_id);
if (muted)
sysconf_write(conv_dac_sc->softmute, 1); /* MUTE */
else
sysconf_write(conv_dac_sc->softmute, 0); /* NORMAL */
return 0;
}
static int
usb_pwr_dwn(struct platform_device *pdev, int host_phy, int pwd)
{
static struct sysconf_field *sc[3];
int port = pdev->id;
/* Power up port */
if (!sc[port])
sc[port] = sysconf_claim(SYS_CFG, 22, 3+port, 3+port,
"usb pwr");
sysconf_write(sc[port], (pwd ? 1 : 0));
return 0;
}
static int
sata_pwd_dwn_req(struct platform_device *pdev, int host_phy, int pwd)
{
static struct sysconf_field *sc[2];
if (cpu_data->cut_major < 3)
return 0;
if (!sc[pdev->id])
sc[pdev->id] = sysconf_claim(SYS_CFG, 22,
1 + pdev->id, 1 + pdev->id, "sata");
sysconf_write(sc[pdev->id], (pwd ? 1 : 0));
return 0;
}
static int snd_stm_conv_dac_sc_set_enabled(int enabled, void *priv)
{
struct snd_stm_conv_dac_sc *conv_dac_sc = priv;
snd_stm_printd(1, "snd_stm_conv_dac_sc_set_enabled(enabled=%d, "
"priv=%p)\n", enabled, priv);
BUG_ON(!conv_dac_sc);
BUG_ON(!snd_stm_magic_valid(conv_dac_sc));
snd_stm_printd(1, "%sabling DAC %s's digital part.\n",
enabled ? "En" : "Dis", conv_dac_sc->bus_id);
if (enabled) {
sysconf_write(conv_dac_sc->nsb, 1); /* NORMAL */
sysconf_write(conv_dac_sc->nrst, 1); /* NORMAL */
} else {
sysconf_write(conv_dac_sc->nrst, 0); /* RESET */
sysconf_write(conv_dac_sc->nsb, 0); /* POWER_DOWN */
}
return 0;
}
static int __init stih415_configure_miphy_uport(void)
{
struct sysconf_field *sc_miphy1_ref_clk,
*sc_sata1_hc_reset, *sc_sata_pcie_sel,
*sc_sata0_hc_reset;
sc_pcie_mp_select = sysconf_claim(SYSCONF(335),
0, 0, "pcie-mp");
BUG_ON(!sc_pcie_mp_select);
/* SATA0_SOFT_RST_N_SATA: sata0_soft_rst_n_sata. */
sc_sata0_hc_reset = sysconf_claim(SYSCONF(377), 7, 7, "MiPHY");
BUG_ON(!sc_sata0_hc_reset);
/* SELECT_SATA: select_sata. */
sc_sata_pcie_sel = sysconf_claim(SYSCONF(333), 1, 1, "MiPHY");
BUG_ON(!sc_sata_pcie_sel);
/* SATAPHY1_OSC_FORCE_EXT: SATAphy1_osc_force_ext. */
sc_miphy1_ref_clk = sysconf_claim(SYSCONF(333), 2, 2, "MiPHY");
BUG_ON(!sc_miphy1_ref_clk);
/*SATA1_SOFT_RST_N_SATA: sata1_soft_rst_n_sata */
sc_sata1_hc_reset = sysconf_claim(SYSCONF(377), 3, 3, "SATA");
BUG_ON(!sc_sata1_hc_reset);
/* Deassert Soft Reset to SATA0 */
sysconf_write(sc_sata0_hc_reset, 1);
/* If the 100MHz xtal for PCIe is present, then the microport interface
* will already have a clock, so there is no need to flip to the 30MHz
* clock here. If it isn't then we have to switch miphy lane 1 to use
* the 30MHz clock, as otherwise we will not be able to talk to lane 0
* since the uport interface itself is clocked from lane1
*/
if (stih415_miphy_modes[1] != PCIE_MODE) {
/* Put MiPHY1 in reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 0);
/* Put SATA1 HC in reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 0);
/* Now switch to Phy interface to SATA HC not PCIe HC */
sysconf_write(sc_sata_pcie_sel, 1);
/* Select the Uport to use MiPHY1 */
stih415_pcie_mp_select(1);
/* Take SATA1 HC out of reset - rst_per_n[30] */
sysconf_write(sc_sata1_hc_reset, 1);
/* MiPHY1 needs to be using the MiPHY0 reference clock */
sysconf_write(sc_miphy1_ref_clk, 1);
/* Take MiPHY1 out of reset - rst_per_n[32] */
sysconf_write(sc_miphy_reset[1], 1);
}
return platform_device_register(&stih415_pcie_mp_device);
}
static void stx7108_restart_sata(int port)
{
/* This part of the code is executed for ESD recovery.
* However...
* It's Not supported on CUT1.0 As we have to reset both Lanes if there
* is a problem with single lane. As the MiPHY Code for JTAG_IF is
* not independent of lanes which will potentially results in a
* recursive resets among lane-0 and lane-1. This behaviour might
* make both disks unavailable.
*/
BUG_ON(cpu_data->cut_major < 2);
/* Reset the SATA Host and MiPHY */
sysconf_write(sc_sata_hc_pwr[port], 1);
sysconf_write(sc_miphy_reset[port], 0);
if (port == 1)
stx7108_pcie_mp_select(1);
msleep(1);
sysconf_write(sc_sata_hc_pwr[port], 0);
sysconf_write(sc_miphy_reset[port], 1);
}
static int
usb_pm_sw_reset(struct platform_device *dev)
{
static struct sysconf_field *sc;
unsigned long reg;
if (!sc)
sc = sysconf_claim(SYS_CFG, 2, 1, 1, "usb reset");
reg = sysconf_read(sc);
if (reg) {
sysconf_write(sc, 0);
mdelay(30);
}
return 0;
}
static void stih415_sata_power(struct stm_device_state *device_state,
int port, enum stm_device_power_state power)
{
int value = (power == stm_device_power_on) ? 0 : 1;
int i;
sysconf_write(sc_sata_hc_pwr[port], value);
for (i = 100; i; --i) {
if (stm_device_sysconf_read(device_state, "SATA_ACK")
== value)
break;
mdelay(10);
}
}
void __init stx7108_configure_usb(int port)
{
static int osc_initialized;
static int configured[ARRAY_SIZE(stx7108_usb_devices)];
struct sysconf_field *sc;
BUG_ON(port < 0 || port >= ARRAY_SIZE(stx7108_usb_devices));
BUG_ON(configured[port]++);
if (!osc_initialized++) {
/* USB2TRIPPHY_OSCIOK */
sc = sysconf_claim(SYS_CFG_BANK4, 44, 6, 6, "USB");
sysconf_write(sc, 1);
}
platform_device_register(&stx7108_usb_devices[port]);
}
static int snd_stm_conv_dac_sc_disconnect(struct snd_device *snd_device)
{
struct snd_stm_conv_dac_sc *conv_dac_sc =
snd_device->device_data;
BUG_ON(!conv_dac_sc);
BUG_ON(!snd_stm_magic_valid(conv_dac_sc));
/* Global power done & mute mode */
sysconf_write(conv_dac_sc->nrst, 0); /* RESET */
sysconf_write(conv_dac_sc->mode, 0); /* DEFAULT */
sysconf_write(conv_dac_sc->nsb, 0); /* POWER_DOWN */
sysconf_write(conv_dac_sc->softmute, 1); /* MUTE */
sysconf_write(conv_dac_sc->pdana, 0); /* POWER_DOWN */
sysconf_write(conv_dac_sc->pndbg, 0); /* POWER_DOWN */
return 0;
}
static int snd_stm_conv_dac_sc_register(struct snd_device *snd_device)
{
struct snd_stm_conv_dac_sc *conv_dac_sc =
snd_device->device_data;
BUG_ON(!conv_dac_sc);
BUG_ON(!snd_stm_magic_valid(conv_dac_sc));
/* Initialize DAC with digital part down, analog up and muted */
sysconf_write(conv_dac_sc->nrst, 0); /* RESET */
sysconf_write(conv_dac_sc->mode, 0); /* DEFAULT */
sysconf_write(conv_dac_sc->nsb, 0); /* POWER_DOWN */
sysconf_write(conv_dac_sc->softmute, 1); /* MUTE */
sysconf_write(conv_dac_sc->pdana, 1); /* NORMAL */
sysconf_write(conv_dac_sc->pndbg, 1); /* NORMAL */
return 0;
}
