static int mv88e1xxx_interrupt_enable(struct cphy *cphy) { /* Enable PHY interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, INTR_ENABLE_MASK); /* Enable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; }
static int mv88e1xxx_interrupt_clear(struct cphy *cphy) { u32 elmer; (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer); if (t1_is_asic(cphy->adapter)) { t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); } return 0; }
static int mv88e1xxx_interrupt_clear(struct cphy *cphy) { u32 elmer; /* Clear PHY interrupts by reading the register. */ (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer); /* Clear Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); } return 0; }
static int mv88e1xxx_interrupt_disable(struct cphy *cphy) { /* Disable all phy interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0); /* Disable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer &= ~ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) { elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4); } (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; }
static int pm3393_interrupt_clear(struct cmac *cmac) { u32 elmer; u32 pl_intr; u32 val32; /* PM3393 - Clearing HW interrupt blocks. Note, this assumes * bit WCIMODE=0 for a clear-on-read. */ pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32); pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32); pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32); pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32); pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32); pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION, &val32); pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32); pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32); /* PM3393 - Global interrupt status */ pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32); /* ELMER - External chip interrupts. */ t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer); elmer |= ELMER0_GP_BIT1; t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer); /* TERMINATOR - PL_INTERUPTS_EXT */ pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE); pl_intr |= F_PL_INTR_EXT; writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE); return 0; }
/* To check the activity LED */ static int my3126_get_link_status(struct cphy *cphy, int *link_ok, int *speed, int *duplex, int *fc) { u32 val; u16 val16; adapter_t *adapter; adapter = cphy->adapter; mdio_read(cphy, 0x1, 0x1, &val); val16 = (u16) val; /* Populate elmer_gpo with the register value */ t1_tpi_read(adapter, A_ELMER0_GPO, &val); cphy->elmer_gpo = val; *link_ok = (val16 & BMSR_LSTATUS); if (*link_ok) { /* Turn on the LED. */ if (is_T2(adapter)) val &= ~(1 << 8); else if (t1_is_T1B(adapter)) val &= ~(1 << 19); } else { /* Turn off the LED. */ if (is_T2(adapter)) val |= (1 << 8); else if (t1_is_T1B(adapter)) val |= (1 << 19); } t1_tpi_write(adapter, A_ELMER0_GPO, val); cphy->elmer_gpo = val; *speed = SPEED_10000; *duplex = DUPLEX_FULL; /* need to add flow control */ if (fc) *fc = PAUSE_RX | PAUSE_TX; return 0; }
/* * External interrupt handler for boards using elmer0. */ int elmer0_ext_intr_handler(adapter_t *adapter) { struct cphy *phy; int phy_cause; u32 cause; t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause); switch (board_info(adapter)->board) { case CHBT_BOARD_N210: case CHBT_BOARD_N110: if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */ phy = adapter->port[0].phy; phy_cause = phy->ops->interrupt_handler(phy); if (phy_cause & cphy_cause_link_change) link_changed(adapter, 0); } break; } t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause); return 0; }
static int pm3393_interrupt_disable(struct cmac *cmac) { u32 elmer; /* PM3393 - Enabling HW interrupt blocks. */ pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); /* PM3393 - Global interrupt enable */ pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); /* ELMER - External chip interrupts. */ t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer &= ~ELMER0_GP_BIT1; t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer); /* TERMINATOR - PL_INTERUPTS_EXT */ /* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level. */ return 0; }
static int mv88x201x_interrupt_clear(struct cphy *cphy) { u32 elmer; u32 val; #ifdef MV88x2010_LINK_STATUS_BUGS /* Required to read twice before clear takes affect. */ (void) mdio_read(cphy, 0x1, 0x9003, &val); (void) mdio_read(cphy, 0x1, 0x9004, &val); (void) mdio_read(cphy, 0x1, 0x9005, &val); /* Read this register after the others above it else * the register doesn't clear correctly. */ (void) mdio_read(cphy, 0x1, 0x1, &val); #endif /* Clear link status. */ (void) mdio_read(cphy, 0x1, 0x1, &val); /* Clear PHY LASI interrupts. */ (void) mdio_read(cphy, 0x1, 0x9005, &val); #ifdef MV88x2010_LINK_STATUS_BUGS /* Do it again. */ (void) mdio_read(cphy, 0x1, 0x9003, &val); (void) mdio_read(cphy, 0x1, 0x9004, &val); #endif /* Clear Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); elmer |= ELMER0_GP_BIT6; (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); } return 0; }
static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) { t1_tpi_write(cmac->adapter, OFFSET(reg), data32); return 0; }