static int arm11_deassert_reset(struct target *target)
{
struct arm11_common *arm11 = target_to_arm11(target);
int retval;
/* be certain SRST is off */
jtag_add_reset(0, 0);
/* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets
* at least DSCR. OMAP24xx doesn't show that problem, though
* SRST-only reset seems to be problematic for other reasons.
* (Secure boot sequences being one likelihood!)
*/
jtag_add_tlr();
CHECK_RETVAL(arm11_poll(target));
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
}
/* maybe restore vector catch config */
if (target->reset_halt && !(arm11->vcr & 1))
CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr));
return ERROR_OK;
}
/* run to exit point. return error if exit point was not reached. */
static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
{
uint32_t pc;
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
* sequence to write register values to the processor and the read them back */
if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
{
return retval;
}
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
return ERROR_TARGET_TIMEOUT;
}
pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
if (exit_point && (pc != exit_point))
{
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
static int msp432_quit(struct flash_bank *bank)
{
struct target *target = bank->target;
struct msp432_bank *msp432_bank = bank->driver_priv;
struct msp432_algo_params algo_params;
int retval;
/* Initialize algorithm parameters to default values */
msp432_init_params(&algo_params);
/* Issue the exit command to the flash helper algorithm */
retval = msp432_exec_cmd(target, &algo_params, FLASH_EXIT);
if (ERROR_OK != retval)
return retval;
(void)msp432_wait_return_code(target);
/* Regardless of the return code, attempt to halt the target */
(void)target_halt(target);
/* Now confirm target halted and clean up from flash helper algorithm */
retval = target_wait_algorithm(target, 0, NULL, 0, NULL, 0, FLASH_TIMEOUT,
&msp432_bank->armv7m_info);
target_free_working_area(target, msp432_bank->working_area);
msp432_bank->working_area = NULL;
return retval;
}
/* wait for execution to complete and check exit point */
static int armv4_5_run_algorithm_completion(struct target *target,
uint32_t exit_point,
int timeout_ms,
void *arch_info)
{
int retval;
struct arm *arm = target_to_arm(target);
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
retval = target_wait_state(target, TARGET_HALTED, 500);
if (retval != ERROR_OK)
return retval;
return ERROR_TARGET_TIMEOUT;
}
/* fast exit: ARMv5+ code can use BKPT */
if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
LOG_WARNING(
"target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
buf_get_u32(arm->pc->value, 0, 32));
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
/* run to exit point. return error if exit point was not reached. */
static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
{
uint32_t pc;
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
* sequence to write register values to the processor and the read them back */
if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
{
return retval;
}
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
return ERROR_TARGET_TIMEOUT;
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (exit_point && (pc != exit_point))
{
LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return ERROR_OK;
}
static int xtensa_deassert_reset(struct target *target)
{
int res;
/* deassert reset lines */
jtag_add_reset(0, 0);
usleep(100000);
res = xtensa_poll(target);
if (res != ERROR_OK)
return res;
if (target->reset_halt) {
/* TODO: work out if possible to halt on reset (I think "no" */
res = target_halt(target);
if (res != ERROR_OK) {
LOG_ERROR("%s: failed to halt afte reset", __func__);
return res;
}
LOG_WARNING("%s: 'reset halt' is not supported for Xtensa. "
"Have halted some time after resetting (not the same thing!)", __func__);
}
LOG_DEBUG("%s", __func__);
return ERROR_OK;
}
int arm926ejs_soft_reset_halt(struct target *target)
{
int retval = ERROR_OK;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
int64_t then = timeval_ms();
int timeout;
while (!(timeout = ((timeval_ms()-then) > 1000))) {
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
embeddedice_read_reg(dbg_stat);
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
} else
break;
if (debug_level >= 1) {
/* do not eat all CPU, time out after 1 se*/
alive_sleep(100);
} else
keep_alive();
}
if (timeout) {
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
/* SVC, ARM state, IRQ and FIQ disabled */
uint32_t cpsr;
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
cpsr &= ~0xff;
cpsr |= 0xd3;
arm_set_cpsr(arm, cpsr);
arm->cpsr->dirty = 1;
/* start fetching from 0x0 */
buf_set_u32(arm->pc->value, 0, 32, 0x0);
arm->pc->dirty = 1;
arm->pc->valid = 1;
retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
if (retval != ERROR_OK)
return retval;
arm926ejs->armv4_5_mmu.mmu_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
int arc_ocd_assert_reset(struct target *target)
{
struct arc32_common *arc32 = target_to_arc32(target);
LOG_DEBUG("target->state: %s", target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
/* allow scripts to override the reset event */
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
register_cache_invalidate(arc32->core_cache);
/* An ARC target might be in halt state after reset, so
* if script requested processor to resume, then it must
* be manually started to ensure that this request
* is satisfied. */
if (target->state == TARGET_HALTED && !target->reset_halt) {
/* Resume the target and continue from the current
* PC register value. */
LOG_DEBUG("Starting CPU execution after reset");
CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
}
target->state = TARGET_RESET;
return ERROR_OK;
}
/* some cores support connecting while srst is asserted
* use that mode is it has been configured */
bool srst_asserted = false;
if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
jtag_add_reset(0, 1);
srst_asserted = true;
}
if (jtag_reset_config & RESET_HAS_SRST) {
/* should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
jtag_add_reset(1, 1);
else if (!srst_asserted)
jtag_add_reset(0, 1);
}
target->state = TARGET_RESET;
jtag_add_sleep(50000);
register_cache_invalidate(arc32->core_cache);
if (target->reset_halt)
CHECK_RETVAL(target_halt(target));
return ERROR_OK;
}
int arc_ocd_assert_reset(struct target *target)
{
struct arc32_common *arc32 = target_to_arc32(target);
LOG_DEBUG("target->state: %s", target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
/* allow scripts to override the reset event */
target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
register_cache_invalidate(arc32->core_cache);
target->state = TARGET_RESET;
return ERROR_OK;
}
/* some cores support connecting while srst is asserted
* use that mode is it has been configured */
bool srst_asserted = false;
if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
(jtag_reset_config & RESET_SRST_NO_GATING)) {
jtag_add_reset(0, 1);
srst_asserted = true;
}
if (jtag_reset_config & RESET_HAS_SRST) {
/* should issue a srst only, but we may have to assert trst as well */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
jtag_add_reset(1, 1);
else if (!srst_asserted)
jtag_add_reset(0, 1);
}
target->state = TARGET_RESET;
jtag_add_sleep(50000);
register_cache_invalidate(arc32->core_cache);
if (target->reset_halt)
CHECK_RETVAL(target_halt(target));
return ERROR_OK;
}
static int nds32_v3m_deassert_reset(struct target *target)
{
int retval;
CHECK_RETVAL(nds32_poll(target));
if (target->state != TARGET_HALTED) {
/* reset only */
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
retval = target_halt(target);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
static int rsp_break_signal(struct tcp_pcb * tp, char * pkt)
{
// int state;
DCC_LOG(LOG_TRACE, "break received, stopping...");
if (target_halt(0) < 0) {
return rsp_error(tp, 1);
}
return 0;
#if 0
if ((state = target_halt_wait(500)) == ERR_TIMEOUT) {
DCC_LOG(LOG_TRACE, "timeout...");
}
if (state == DBG_ST_HALTED) {
DCC_LOG(LOG_TRACE, "halted");
return rsp_signal(tp, pkt, SIGTRAP);
}
return rsp_msg(tp, pkt, "YARD-ICE: target_halt failed!");
#endif
}
/** Waits for an algorithm in the target. */
int armv7m_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t exit_point, int timeout_ms,
void *arch_info)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
int retval = ERROR_OK;
uint32_t pc;
/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
* at the exit point */
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
{
LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
/* If the target fails to halt due to the breakpoint, force a halt */
if (retval != ERROR_OK || target->state != TARGET_HALTED)
{
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
{
return retval;
}
return ERROR_TARGET_TIMEOUT;
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (exit_point && (pc != exit_point))
{
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" PRIx32 , pc, exit_point);
return ERROR_TARGET_TIMEOUT;
}
/* Read memory values to mem_params[] */
for (int i = 0; i < num_mem_params; i++)
{
if (mem_params[i].direction != PARAM_OUT)
if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
{
return retval;
}
}
/* Copy core register values to reg_params[] */
for (int i = 0; i < num_reg_params; i++)
{
if (reg_params[i].direction != PARAM_OUT)
{
struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
return ERROR_INVALID_ARGUMENTS;
}
if (reg->size != reg_params[i].size)
{
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
return ERROR_INVALID_ARGUMENTS;
}
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
}
}
for (int i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
{
uint32_t regvalue;
regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i])
{
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
armv7m->core_cache->reg_list[i].name, armv7m_algorithm_info->context[i]);
buf_set_u32(armv7m->core_cache->reg_list[i].value,
0, 32, armv7m_algorithm_info->context[i]);
armv7m->core_cache->reg_list[i].valid = 1;
armv7m->core_cache->reg_list[i].dirty = 1;
}
}
armv7m->core_mode = armv7m_algorithm_info->core_mode;
return retval;
}
static int rsp_last_signal(struct gdb_rspd * gdb, struct tcp_pcb * tp,
char * pkt, int len)
{
int state;
state = target_status();
if (state < DBG_ST_CONNECTED) {
DCC_LOG(LOG_WARNING, "target not connected!");
return rsp_error(tp, state);
}
if (state != DBG_ST_HALTED) {
DCC_LOG(LOG_TRACE, "running");
if ((state = target_halt(0)) < 0) {
DCC_LOG(LOG_WARNING, "target_halt() failed!");
rsp_msg(tp, pkt, "YARD-ICE: halt fail\n");
return rsp_error(tp, 1);
}
if ((state = target_halt_wait(500)) == ERR_TIMEOUT) {
DCC_LOG(LOG_TRACE, "timeout...");
rsp_msg(tp, pkt, "YARD-ICE: target_halt failed!");
return rsp_error(tp, 1);
}
}
if (state == DBG_ST_HALTED) {
DCC_LOG(LOG_TRACE, "halted");
thinkos_flag_clr(gdb->run_flag);
return rsp_signal(tp, pkt, SIGTRAP);
}
switch (state) {
case DBG_ST_ERROR:
rsp_msg(tp, pkt, "YARD-ICE: error state\n");
break;
case DBG_ST_OUTOFSYNC:
DCC_LOG(LOG_TRACE, "out of sync");
rsp_msg(tp, pkt, "YARD-ICE: Out of sync\n");
break;
case DBG_ST_BUSY:
DCC_LOG(LOG_TRACE, "busy...");
rsp_msg(tp, pkt, "YARD-ICE: busy ... \n");
break;
case DBG_ST_UNDEF:
rsp_msg(tp, pkt, "YARD-ICE: undefined state\n");
break;
case DBG_ST_UNCONNECTED:
DCC_LOG(LOG_TRACE, "unconnected");
rsp_msg(tp, pkt, "YARD-ICE: unconnected ?\n");
break;
case DBG_ST_CONNECTED:
DCC_LOG(LOG_TRACE, "connected");
rsp_msg(tp, pkt, "YARD-ICE: connected (busy)\n");
break;
case DBG_ST_RUNNING:
DCC_LOG(LOG_TRACE, "running");
rsp_msg(tp, pkt, "YARD-ICE: running\n");
thinkos_flag_set(gdb->run_flag);
break;
default:
DCC_LOG1(LOG_WARNING, "unknown state: %d", state);
rsp_msg(tp, pkt, "YARD-ICE: unknown state, bailing out!\n");
return -1;
}
return rsp_error(tp, 1);
}
