static int arm_default_mcr(struct target *target, int cpnum,
uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm,
uint32_t value)
{
LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
return ERROR_FAIL;
}
/**
* Probe EmbeddedICE module and set up local records of its registers.
* Different versions of the modules have different capabilities, such as
* hardware support for vector_catch, single stepping, and monitor mode.
*/
struct reg_cache *embeddedice_build_reg_cache(struct target *target,
struct arm7_9_common *arm7_9)
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = NULL;
struct embeddedice_reg *arch_info = NULL;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
int i;
int eice_version = 0;
/* vector_catch isn't always present */
if (!arm7_9->has_vector_catch)
num_regs--;
/* the actual registers are kept in two arrays */
reg_list = calloc(num_regs, sizeof(struct reg));
arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
/* fill in values for the reg cache */
reg_cache->name = "EmbeddedICE registers";
reg_cache->next = NULL;
reg_cache->reg_list = reg_list;
reg_cache->num_regs = num_regs;
/* FIXME the second watchpoint unit on Feroceon and Dragonite
* seems not to work ... we should have a way to not set up
* its four registers here!
*/
/* set up registers */
for (i = 0; i < num_regs; i++) {
reg_list[i].name = eice_regs[i].name;
reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].type = &eice_reg_type;
arch_info[i].addr = eice_regs[i].addr;
arch_info[i].jtag_info = jtag_info;
}
/* identify EmbeddedICE version by reading DCC control register */
embeddedice_read_reg(®_list[EICE_COMMS_CTRL]);
retval = jtag_execute_queue();
if (retval != ERROR_OK) {
for (i = 0; i < num_regs; i++)
free(reg_list[i].value);
free(reg_list);
free(reg_cache);
free(arch_info);
return NULL;
}
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
LOG_INFO("Embedded ICE version %d", eice_version);
switch (eice_version) {
case 1:
/* ARM7TDMI r3, ARM7TDMI-S r3
*
* REVISIT docs say ARM7TDMI-S r4 uses version 1 but
* that it has 6-bit CTRL and 5-bit STAT... doc bug?
* ARM7TDMI r4 docs say EICE v4.
*/
reg_list[EICE_DBG_CTRL].size = 3;
reg_list[EICE_DBG_STAT].size = 5;
break;
case 2:
/* ARM9TDMI */
reg_list[EICE_DBG_CTRL].size = 4;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
break;
case 3:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 4:
/* ARM7TDMI r4 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
case 5:
/* ARM9E-S rev 1 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 6:
/* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 10;
/* DBG_STAT has MOE bits */
arm7_9->has_monitor_mode = 1;
break;
case 7:
LOG_ERROR("EmbeddedICE v%d handling might be broken",
eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
default:
/*
* The Feroceon implementation has the version number
* in some unusual bits. Let feroceon.c validate it
* and do the appropriate setup itself.
*/
if (strcmp(target_type_name(target), "feroceon") == 0 ||
strcmp(target_type_name(target), "dragonite") == 0)
break;
LOG_ERROR("unknown EmbeddedICE version "
"(comms ctrl: 0x%8.8" PRIx32 ")",
buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
}
/* On Feroceon and Dragonite the second unit is seemingly missing. */
LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
target_name(target), arm7_9->wp_available_max,
(arm7_9->wp_available_max != 1) ? "s" : "");
return reg_cache;
}
int rtos_create(Jim_GetOptInfo *goi, struct target * target)
{
int x;
char *cp;
if (! goi->isconfigure) {
if (goi->argc != 0) {
if (goi->argc != 0) {
Jim_WrongNumArgs(goi->interp,
goi->argc, goi->argv,
"NO PARAMS");
return JIM_ERR;
}
Jim_SetResultString(goi->interp,
target_type_name(target), -1);
}
}
if (target->rtos) {
free((void *)(target->rtos));
}
// e = Jim_GetOpt_String(goi, &cp, NULL);
// target->rtos = strdup(cp);
Jim_GetOpt_String(goi, &cp, NULL);
/* now does target type exist */
if ( 0 == strcmp( cp, "auto") )
{
// auto detection of RTOS
target->rtos_auto_detect = true;
x = 0;
}
else
{
for (x = 0 ; rtos_types[x] ; x++) {
if (0 == strcmp(cp, rtos_types[x]->name)) {
/* found */
break;
}
}
if (rtos_types[x] == NULL) {
Jim_SetResultFormatted(goi->interp, "Unknown rtos type %s, try one of ", cp);
for (x = 0 ; rtos_types[x] ; x++) {
if (rtos_types[x + 1]) {
Jim_AppendStrings(goi->interp,
Jim_GetResult(goi->interp),
rtos_types[x]->name,
", ", NULL);
} else {
Jim_AppendStrings(goi->interp,
Jim_GetResult(goi->interp),
" or ",
rtos_types[x]->name,NULL);
}
}
return JIM_ERR;
}
}
/* Create it */
target->rtos = calloc(1,sizeof(struct rtos));
target->rtos->type = rtos_types[x];
target->rtos->current_thread = 0;
target->rtos->symbols = NULL;
target->rtos->target = target;
if ( 0 != strcmp( cp, "auto") )
{
target->rtos->type->create( target );
}
return JIM_OK;
}
