static int hotplug_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
if (action == CPU_ONLINE)
tegra3_register_wake_timer((unsigned int)cpu);
else if (action == CPU_DOWN_PREPARE)
tegra3_unregister_wake_timer((unsigned int)cpu);
return NOTIFY_OK;
}
void __init tegra3_init_timer(u32 *offset, int *irq)
{
unsigned long rate = tegra_clk_measure_input_freq();
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
/* For T30.A01 use INT_TMR_SHARED instead of INT_TMR6 for CPU3. */
if ((tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) &&
(tegra_get_revision() == TEGRA_REVISION_A01))
tegra_lp2wake_irq[3].irq = INT_TMR_SHARED;
#endif
tegra3_register_wake_timer(0);
#endif
*offset = TIMER1_OFFSET;
*irq = INT_TMR1;
}
static int hotplug_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
switch (action) {
case CPU_ONLINE:
tegra3_register_wake_timer((unsigned int)cpu);
break;
case CPU_ONLINE_FROZEN:
tegra3_resume_wake_timer((unsigned int)cpu);
break;
case CPU_DOWN_PREPARE:
tegra3_unregister_wake_timer((unsigned int)cpu);
break;
case CPU_DOWN_PREPARE_FROZEN:
tegra3_suspend_wake_timer((unsigned int)cpu);
break;
default:
break;
}
return NOTIFY_OK;
}
