static void tegra_dc_rgb_enable(struct tegra_dc *dc) { int i; u32 out_sel_pintable[ARRAY_SIZE(tegra_dc_rgb_enable_out_sel_pintable)]; tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, DC_CMD_DISPLAY_POWER_CONTROL); tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); if (dc->out->out_pins) { tegra_dc_set_out_pin_polars(dc, dc->out->out_pins, dc->out->n_out_pins); tegra_dc_write_table(dc, tegra_dc_rgb_enable_partial_pintable); } else { tegra_dc_write_table(dc, tegra_dc_rgb_enable_pintable); } memcpy(out_sel_pintable, tegra_dc_rgb_enable_out_sel_pintable, sizeof(tegra_dc_rgb_enable_out_sel_pintable)); if (dc->out && dc->out->out_sel_configs) { u8 *out_sels = dc->out->out_sel_configs; for (i = 0; i < dc->out->n_out_sel_configs; i++) { switch (out_sels[i]) { case TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_M1; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_LD21; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_PM1; break; default: dev_err(&dc->ndev->dev, "Invalid pin config[%d]: %d\n", i, out_sels[i]); break; } } } tegra_dc_write_table(dc, out_sel_pintable); /* Inform DC register updated */ tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); }
static void tegra_dc_rgb_enable(struct tegra_dc *dc) { int i; u32 out_sel_pintable[ARRAY_SIZE(tegra_dc_rgb_enable_out_sel_pintable)]; tegra_dc_io_start(dc); tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, DC_CMD_DISPLAY_POWER_CONTROL); tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); if (dc->out->out_pins) { tegra_dc_set_out_pin_polars(dc, dc->out->out_pins, dc->out->n_out_pins); tegra_dc_write_table(dc, tegra_dc_rgb_enable_partial_pintable); } else { tegra_dc_write_table(dc, tegra_dc_rgb_enable_pintable); } memcpy(out_sel_pintable, tegra_dc_rgb_enable_out_sel_pintable, sizeof(tegra_dc_rgb_enable_out_sel_pintable)); /* The display panel sub-board used on FPGA platforms (panel 86) is non-standard. It expects the Data Enable signal on the WR pin instead of the DE pin. */ if (tegra_platform_is_fpga()) out_sel_pintable[3*2+1] = 0x00200000; if (dc->out && dc->out->out_sel_configs) { u8 *out_sels = dc->out->out_sel_configs; for (i = 0; i < dc->out->n_out_sel_configs; i++) { switch (out_sels[i]) { case TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_M1; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_LD21; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_PM1; break; default: dev_err(&dc->ndev->dev, "Invalid pin config[%d]: %d\n", i, out_sels[i]); break; } } } tegra_dc_write_table(dc, out_sel_pintable); /* Inform DC register updated */ tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); tegra_dc_io_end(dc); }
void tegra_dc_rgb_enable(struct tegra_dc *dc) { int i; u32 out_sel_pintable[ARRAY_SIZE(tegra_dc_rgb_enable_out_sel_pintable)]; tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE, DC_CMD_DISPLAY_POWER_CONTROL); tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); if (tegra3_get_project_id()==0x4){ printk("Check tegra_dc_rgb_enable \n"); dc->out->out_pins = cardhu_dc_out_pins; dc->out->n_out_pins = ARRAY_SIZE(cardhu_dc_out_pins); } if (dc->out->out_pins) { printk("Check set polarity \n"); tegra_dc_set_out_pin_polars(dc, dc->out->out_pins, dc->out->n_out_pins); tegra_dc_write_table(dc, tegra_dc_rgb_enable_partial_pintable); } else { tegra_dc_write_table(dc, tegra_dc_rgb_enable_pintable); } memcpy(out_sel_pintable, tegra_dc_rgb_enable_out_sel_pintable, sizeof(tegra_dc_rgb_enable_out_sel_pintable)); if (dc->out && dc->out->out_sel_configs) { u8 *out_sels = dc->out->out_sel_configs; for (i = 0; i < dc->out->n_out_sel_configs; i++) { switch (out_sels[i]) { case TEGRA_PIN_OUT_CONFIG_SEL_LM1_M1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_M1; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_LD21: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_LD21; break; case TEGRA_PIN_OUT_CONFIG_SEL_LM1_PM1: out_sel_pintable[5*2+1] = (out_sel_pintable[5*2+1] & ~PIN5_LM1_LCD_M1_OUTPUT_MASK) | PIN5_LM1_LCD_M1_OUTPUT_PM1; break; default: dev_err(&dc->ndev->dev, "Invalid pin config[%d]: %d\n", i, out_sels[i]); break; } } } tegra_dc_write_table(dc, out_sel_pintable); }