void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor,
const struct tegra_dc_dp_link_config *link_cfg)
{
tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, NV_SOR_PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, NV_SOR_POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, NV_SOR_LVDS, 0);
tegra_dc_sor_set_link_bandwidth(sor, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(sor, link_cfg->lane_count);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
NV_SOR_DP_PADCTL_TX_PU_ENABLE |
2 << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, NV_SOR_DP_PADCTL(sor->portnum),
0xf0, 0x0);
}
void tegra_dc_sor_set_lane_parm(struct udevice *dev,
const struct tegra_dp_link_config *link_cfg)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),
link_cfg->drive_current);
tegra_sor_writel(sor, PR(sor->portnum),
link_cfg->preemphasis);
tegra_sor_writel(sor, POSTCURSOR(sor->portnum),
link_cfg->postcursor);
tegra_sor_writel(sor, LVDS, 0);
tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);
tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),
DP_PADCTL_TX_PU_ENABLE |
DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK,
DP_PADCTL_TX_PU_ENABLE |
2 << DP_PADCTL_TX_PU_VALUE_SHIFT);
/* Precharge */
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);
udelay(20);
tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);
}
static int tegra_dc_sor_power_dplanes(struct tegra_dc_sor_data *sor,
u32 lane_count, int pu)
{
u32 reg_val;
reg_val = tegra_sor_readl(sor, NV_SOR_DP_PADCTL(sor->portnum));
if (pu) {
switch (lane_count) {
case 4:
reg_val |= (NV_SOR_DP_PADCTL_PD_TXD_3_NO |
NV_SOR_DP_PADCTL_PD_TXD_2_NO);
/* fall through */
case 2:
reg_val |= NV_SOR_DP_PADCTL_PD_TXD_1_NO;
case 1:
reg_val |= NV_SOR_DP_PADCTL_PD_TXD_0_NO;
break;
default:
printk(BIOS_ERR,
"dp: invalid lane number %d\n", lane_count);
return -1;
}
tegra_sor_writel(sor, NV_SOR_DP_PADCTL(sor->portnum), reg_val);
tegra_dc_sor_set_lane_count(sor, lane_count);
}
return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
}
static int tegra_dc_sor_power_dplanes(struct udevice *dev,
u32 lane_count, int pu)
{
struct tegra_dc_sor_data *sor = dev_get_priv(dev);
u32 reg_val;
reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));
if (pu) {
switch (lane_count) {
case 4:
reg_val |= (DP_PADCTL_PD_TXD_3_NO |
DP_PADCTL_PD_TXD_2_NO);
/* fall through */
case 2:
reg_val |= DP_PADCTL_PD_TXD_1_NO;
case 1:
reg_val |= DP_PADCTL_PD_TXD_0_NO;
break;
default:
debug("dp: invalid lane number %d\n", lane_count);
return -1;
}
tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);
tegra_dc_sor_set_lane_count(dev, lane_count);
}
return tegra_dc_sor_enable_lane_sequencer(sor, pu, 0);
}
