void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
{
int pclk;
if (dc->out->type == TEGRA_DC_OUT_HDMI) {
unsigned long rate;
struct clk *pll_d_out0_clk =
clk_get_sys(NULL, "pll_d_out0");
struct clk *pll_d_clk =
clk_get_sys(NULL, "pll_d");
if (dc->mode.pclk > 70000000)
rate = 594000000;
else if (dc->mode.pclk >= 27000000)
rate = 216000000;
else
rate = 252000000;
if (rate != clk_get_rate(pll_d_clk))
clk_set_rate(pll_d_clk, rate);
if (clk_get_parent(clk) != pll_d_out0_clk)
clk_set_parent(clk, pll_d_out0_clk);
}
pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
tegra_dvfs_set_rate(clk, pclk);
}
static void _tegra_dc_disable(struct tegra_dc *dc)
{
int i;
disable_irq(dc->irq);
if (dc->out_ops && dc->out_ops->disable)
dc->out_ops->disable(dc);
clk_disable(dc->emc_clk);
clk_disable(dc->clk);
tegra_dvfs_set_rate(dc->clk, 0);
if (dc->out && dc->out->disable)
dc->out->disable();
/* flush any pending syncpt waits */
for (i = 0; i < dc->n_windows; i++) {
while (dc->syncpt[i].min < dc->syncpt[i].max) {
dc->syncpt[i].min++;
nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
dc->syncpt[i].id);
}
}
tegra_dc_io_end(dc);
}
void tegra_dc_clk_enable(struct tegra_dc *dc)
{
if (!tegra_is_clk_enabled(dc->clk)) {
clk_enable(dc->clk);
tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
}
}
void tegra_dc_clk_disable(struct tegra_dc *dc)
{
if (tegra_is_clk_enabled(dc->clk)) {
clk_disable(dc->clk);
tegra_dvfs_set_rate(dc->clk, 0);
}
}
void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
{
int pclk;
if (dc->out_ops->setup_clk)
pclk = dc->out_ops->setup_clk(dc, clk);
else
pclk = 0;
WARN_ONCE(!pclk, "pclk is 0\n");
tegra_dvfs_set_rate(clk, pclk);
}
