static int tegra_lcd_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
int type = DCACHE_OFF;
/* Initialize the Tegra display controller */
if (tegra_display_probe(blob, priv, (void *)plat->base)) {
printf("%s: Failed to probe display driver\n", __func__);
return -1;
}
tegra_lcd_check_next_stage(blob, priv, 1);
/* Set up the LCD caching as requested */
if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
type = DCACHE_WRITETHROUGH;
else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
type = DCACHE_WRITEBACK;
mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
/* Enable flushing after LCD writes if requested */
video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
uc_priv->xsize = priv->width;
uc_priv->ysize = priv->height;
uc_priv->bpix = priv->log2_bpp;
debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
plat->size);
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_LCD
/* Make sure we finish initing the LCD */
tegra_lcd_check_next_stage(gd->fdt_blob, 1);
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_LCD
/* Make sure we finish initing the LCD */
tegra_lcd_check_next_stage(gd->fdt_blob, 1);
#endif
#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
if (tegra_cpu_is_non_secure()) {
printf("CPU is in NS mode\n");
setenv("cpu_ns_mode", "1");
} else {
setenv("cpu_ns_mode", "");
}
#endif
start_cpu_fan();
return 0;
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
__maybe_unused int err;
/* Do clocks and UART first so that printf() works */
clock_init();
clock_verify();
#ifdef CONFIG_FDT_SPI
pin_mux_spi();
spi_init();
#endif
#ifdef CONFIG_PWM_TEGRA
if (pwm_init(gd->fdt_blob))
debug("%s: Failed to init pwm\n", __func__);
#endif
#ifdef CONFIG_LCD
pin_mux_display();
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
power_det_init();
#ifdef CONFIG_TEGRA_I2C
#ifndef CONFIG_SYS_I2C_INIT_BOARD
#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
#endif
i2c_init_board();
# ifdef CONFIG_TEGRA_PMU
if (pmu_set_nominal())
debug("Failed to select nominal voltages\n");
# ifdef CONFIG_TEGRA_CLOCK_SCALING
err = board_emc_init();
if (err)
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
#endif /* CONFIG_TEGRA_I2C */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_usb();
board_usb_init(gd->fdt_blob);
#endif
#ifdef CONFIG_LCD
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
#ifdef CONFIG_TEGRA_NAND
pin_mux_nand();
#endif
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
return 0;
}
static int
twostop_init(struct twostop_fmap *fmap, firmware_storage_t *file,
void **gbbp, size_t gbb_size, crossystem_data_t *cdata,
void *vb_shared_data)
{
struct vboot_flag_details wpsw, recsw, devsw, oprom;
GoogleBinaryBlockHeader *gbbh;
uint8_t hardware_id[ID_LEN];
#ifndef CONFIG_HARDWARE_MAPPED_SPI
uint8_t readonly_firmware_id[ID_LEN];
#else
uint8_t *readonly_firmware_id;
#endif
int oprom_matters = 0;
int ret = -1;
void *gbb;
bootstage_mark_name(BOOTSTAGE_VBOOT_TWOSTOP_INIT, "twostop_init");
if (vboot_flag_fetch(VBOOT_FLAG_WRITE_PROTECT, &wpsw) ||
vboot_flag_fetch(VBOOT_FLAG_RECOVERY, &recsw) ||
vboot_flag_fetch(VBOOT_FLAG_DEVELOPER, &devsw) ||
vboot_flag_fetch(VBOOT_FLAG_OPROM_LOADED, &oprom)) {
VBDEBUG("failed to fetch gpio\n");
return -1;
}
vboot_flag_dump(VBOOT_FLAG_WRITE_PROTECT, &wpsw);
vboot_flag_dump(VBOOT_FLAG_RECOVERY, &recsw);
vboot_flag_dump(VBOOT_FLAG_DEVELOPER, &devsw);
vboot_flag_dump(VBOOT_FLAG_OPROM_LOADED, &oprom);
if (cros_fdtdec_config_has_prop(gd->fdt_blob, "oprom-matters")) {
VBDEBUG("FDT says oprom-matters\n");
oprom_matters = 1;
}
if (!fmap->readonly.fmap.length &&
cros_fdtdec_flashmap(gd->fdt_blob, fmap)) {
VBDEBUG("failed to decode fmap\n");
return -1;
}
dump_fmap(fmap);
/* We revert the decision of using firmware_storage_open_twostop() */
if (firmware_storage_open_spi(file)) {
VBDEBUG("failed to open firmware storage\n");
return -1;
}
/* Read read-only firmware ID */
if (file->read(file, fmap->readonly.firmware_id.offset,
MIN(sizeof(readonly_firmware_id),
fmap->readonly.firmware_id.length),
BT_EXTRA readonly_firmware_id)) {
VBDEBUG("failed to read firmware ID\n");
readonly_firmware_id[0] = '\0';
}
VBDEBUG("read-only firmware id: \"%s\"\n", readonly_firmware_id);
/* Load basic parts of gbb blob */
#ifdef CONFIG_HARDWARE_MAPPED_SPI
if (gbb_init(gbbp, file, fmap->readonly.gbb.offset, gbb_size)) {
VBDEBUG("failed to read gbb\n");
goto out;
}
gbb = *gbbp;
#else
gbb = *gbbp;
if (gbb_init(gbb, file, fmap->readonly.gbb.offset, gbb_size)) {
VBDEBUG("failed to read gbb\n");
goto out;
}
#endif
gbbh = (GoogleBinaryBlockHeader *)gbb;
memcpy(hardware_id, gbb + gbbh->hwid_offset,
MIN(sizeof(hardware_id), gbbh->hwid_size));
VBDEBUG("hardware id: \"%s\"\n", hardware_id);
/* Initialize crossystem data */
/*
* TODO There is no readwrite EC firmware on our current ARM boards. But
* we should have a mechanism to probe (or acquire this information from
* the device tree) whether the active EC firmware is R/O or R/W.
*/
if (crossystem_data_init(cdata,
&wpsw, &recsw, &devsw, &oprom,
oprom_matters,
fmap->readonly.fmap.offset,
ACTIVE_EC_FIRMWARE_RO,
hardware_id,
readonly_firmware_id)) {
VBDEBUG("failed to init crossystem data\n");
goto out;
}
ret = 0;
#ifdef CONFIG_VIDEO_TEGRA
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
#ifdef CONFIG_EXYNOS_DISPLAYPORT
exynos_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
out:
if (ret)
file->close(file);
return ret;
}
static VbError_t
twostop_init_vboot_library(firmware_storage_t *file, void *gbb,
uint32_t gbb_offset, size_t gbb_size,
crossystem_data_t *cdata, VbCommonParams *cparams)
{
VbError_t err;
VbInitParams iparams;
int virtual_dev_switch =
cros_fdtdec_config_has_prop(gd->fdt_blob,
"virtual-dev-switch");
#ifdef CONFIG_MKBP
struct mkbp_dev *mdev = board_get_mkbp_dev();
#endif
memset(&iparams, 0, sizeof(iparams));
iparams.flags = check_ro_normal_support();
#ifdef CONFIG_MKBP
if (mdev) {
uint32_t ec_events = 0;
const uint32_t kb_rec_mask =
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
/* Read keyboard recovery flag from EC, then clear it */
if (mkbp_get_host_events(mdev, &ec_events)) {
/*
* TODO: what can we do if that fails? Request
* recovery? We don't simply want to fail, because
* that'll prevent us from going into recovery mode.
* We don't want to go into recovery mode
* automatically, because that'll break snow.
*/
VBDEBUG("VbInit: unable to read EC events\n");
ec_events = 0;
}
if (ec_events & kb_rec_mask) {
iparams.flags |= VB_INIT_FLAG_REC_BUTTON_PRESSED;
if (mkbp_clear_host_events(mdev, kb_rec_mask))
VBDEBUG("VbInit: unable to clear "
"EC KB recovery event\n");
}
}
#endif
if (cdata->boot_write_protect_switch)
iparams.flags |= VB_INIT_FLAG_WP_ENABLED;
if (cdata->boot_recovery_switch)
iparams.flags |= VB_INIT_FLAG_REC_BUTTON_PRESSED;
if (cdata->boot_developer_switch)
iparams.flags |= VB_INIT_FLAG_DEV_SWITCH_ON;
if (cdata->boot_oprom_loaded)
iparams.flags |= VB_INIT_FLAG_OPROM_LOADED;
if (cdata->oprom_matters)
iparams.flags |= VB_INIT_FLAG_OPROM_MATTERS;
if (virtual_dev_switch)
iparams.flags |= VB_INIT_FLAG_VIRTUAL_DEV_SWITCH;
if (cros_fdtdec_config_has_prop(gd->fdt_blob, "ec-software-sync"))
iparams.flags |= VB_INIT_FLAG_EC_SOFTWARE_SYNC;
if (cros_fdtdec_config_has_prop(gd->fdt_blob, "ec-slow-update"))
iparams.flags |= VB_INIT_FLAG_EC_SLOW_UPDATE;
if (flash_sw_wp_is_enabled(file))
iparams.flags |= VB_INIT_FLAG_SW_WP_ENABLED;
VBDEBUG("iparams.flags: %08x\n", iparams.flags);
if ((err = VbInit(cparams, &iparams))) {
VBDEBUG("VbInit: %u\n", err);
/*
* If vboot wants EC to reboot to RO, make request now,
* because there isn't a clear path to pass this request
* through to do_vboot_twostop().
*/
if (err == VBERROR_EC_REBOOT_TO_RO_REQUIRED)
request_ec_reboot_to_ro();
return err;
}
#ifdef CONFIG_VIDEO_TEGRA
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
#ifdef CONFIG_EXYNOS_DISPLAYPORT
exynos_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
VBDEBUG("iparams.out_flags: %08x\n", iparams.out_flags);
if (virtual_dev_switch) {
cdata->boot_developer_switch =
(iparams.out_flags & VB_INIT_OUT_ENABLE_DEVELOPER) ?
1 : 0;
VBDEBUG("cdata->boot_developer_switch=%d\n",
cdata->boot_developer_switch);
}
if (iparams.out_flags & VB_INIT_OUT_CLEAR_RAM)
wipe_unused_memory(cdata, cparams);
/* Load required information of GBB */
if (iparams.out_flags & VB_INIT_OUT_ENABLE_DISPLAY) {
if (gbb_read_bmp_block(gbb, file, gbb_offset, gbb_size))
return VBERROR_INVALID_GBB;
have_read_gbb_bmp_block = 1;
}
if (cdata->boot_developer_switch ||
iparams.out_flags & VB_INIT_OUT_ENABLE_RECOVERY) {
if (gbb_read_recovery_key(gbb, file, gbb_offset, gbb_size))
return VBERROR_INVALID_GBB;
}
return VBERROR_SUCCESS;
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
__maybe_unused int err;
__maybe_unused int board_id;
/* Do clocks and UART first so that printf() works */
clock_init();
clock_verify();
tegra_gpu_config();
#ifdef CONFIG_TEGRA_SPI
pin_mux_spi();
#endif
#ifdef CONFIG_PWM_TEGRA
if (pwm_init(gd->fdt_blob))
debug("%s: Failed to init pwm\n", __func__);
#endif
#ifdef CONFIG_LCD
pin_mux_display();
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
/* boot param addr */
gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
power_det_init();
#ifdef CONFIG_SYS_I2C_TEGRA
# ifdef CONFIG_TEGRA_PMU
if (pmu_set_nominal())
debug("Failed to select nominal voltages\n");
# ifdef CONFIG_TEGRA_CLOCK_SCALING
err = board_emc_init();
if (err)
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
#ifdef CONFIG_AS3722_POWER
err = as3722_init(NULL);
if (err && err != -ENODEV)
return err;
#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
pin_mux_usb();
#endif
#ifdef CONFIG_LCD
board_id = tegra_board_id();
err = tegra_lcd_pmic_init(board_id);
if (err)
return err;
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
#ifdef CONFIG_TEGRA_NAND
pin_mux_nand();
#endif
tegra_xusb_padctl_init(gd->fdt_blob);
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
return nvidia_board_init();
}
