static void __init tegra_dt_init_irq(void)
{
tegra_pmc_init_irq();
tegra_init_irq();
irqchip_init();
tegra_legacy_irq_syscore_init();
}
static int __init tegra_gic_of_init(struct device_node *node,
struct device_node *parent)
{
int i;
struct device_node *arm_gic_np =
of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
struct device_node *tegra_gic_np =
of_find_compatible_node(NULL, NULL, "nvidia,tegra-gic");
tegra_wakeup_table_init();
gic_dist_base = of_iomap(arm_gic_np, 0);
gic_cpu_base = of_iomap(arm_gic_np, 1);
gic_version = (readl(gic_dist_base + 0xFE8) & 0xF0) >> 4;
/* Retrieve # of ictrls from DT and fallback to gic dist */
if (of_property_read_u32(tegra_gic_np, "num-ictrls", &num_ictlrs))
num_ictlrs = readl_relaxed(gic_dist_base + GIC_DIST_CTR) & 0x1f;
pr_info("the number of interrupt controllers found is %d", num_ictlrs);
ictlr_reg_base = kzalloc(sizeof(void *) * num_ictlrs, GFP_KERNEL);
tegra_clocks_init();
for (i = 0; i < num_ictlrs; i++) {
ictlr_reg_base[i] = of_iomap(node, i);
if (!ictlr_reg_base[i]) {
pr_info("failed to get the right register\n");
return -EINVAL;
}
writel(~0, ictlr_reg_base[i] + ICTLR_CPU_IER_CLR);
writel(0, ictlr_reg_base[i] + ICTLR_CPU_IEP_CLASS);
writel(~0, ictlr_reg_base[i] + ICTLR_CPU_IEP_FIR_CLR);
}
gic_arch_extn.irq_ack = tegra_ack;
gic_arch_extn.irq_eoi = tegra_eoi;
gic_arch_extn.irq_mask = tegra_mask;
gic_arch_extn.irq_unmask = tegra_unmask;
gic_arch_extn.irq_retrigger = tegra_retrigger;
gic_arch_extn.irq_set_type = tegra_set_type;
gic_arch_extn.irq_set_wake = tegra_set_wake;
gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
#ifdef CONFIG_PM_SLEEP
tegra_legacy_irq_syscore_init();
if (gic_version == GIC_V2)
cpu_pm_register_notifier(&tegra_gic_notifier_block);
#endif
#if !defined(CONFIG_TRUSTED_FOUNDATIONS) && \
defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER)
tegra_gic_dist_init();
#endif
return 0;
}
