static void tegra2_wake_reset_cpu(int cpu)
{
u32 reg;
BUG_ON(cpu == 0);
BUG_ON(cpu == smp_processor_id());
tegra_pen_lock();
tegra2_cpu_clear_resettable();
/* enable cpu clock on cpu */
reg = readl(clk_rst + 0x4c);
writel(reg & ~(1 << (8 + cpu)),
clk_rst + CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
/* take the CPU out of reset */
reg = 0x1111 << cpu;
writel(reg, clk_rst +
CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
/* unhalt the cpu */
flowctrl_writel(0, FLOW_CTRL_HALT_CPU(1));
tegra_pen_unlock();
}
static int tegra20_reset_sleeping_cpu_1(void)
{
int ret = 0;
tegra_pen_lock();
if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
tegra20_cpu_shutdown(1);
else
ret = -EINVAL;
tegra_pen_unlock();
return ret;
}
static void tegra20_wake_cpu1_from_reset(void)
{
tegra_pen_lock();
tegra20_cpu_clear_resettable();
/* enable cpu clock on cpu */
tegra_enable_cpu_clock(1);
/* take the CPU out of reset */
tegra_cpu_out_of_reset(1);
/* unhalt the cpu */
flowctrl_write_cpu_halt(1, 0);
tegra_pen_unlock();
}
static int tegra2_reset_sleeping_cpu(int cpu)
{
int ret = 0;
BUG_ON(cpu == 0);
BUG_ON(cpu == smp_processor_id());
tegra_pen_lock();
if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
tegra2_cpu_reset(cpu);
else
ret = -EINVAL;
tegra_pen_unlock();
return ret;
}
