int main(void) { #ifdef WILDDOG_SELFTEST return test_ram(); #endif }
int main(void) { u2_init(); putstr("\nFactory Test, Board Rev 3.0\n"); bool ok = true; unsigned char maj = HW_REV_MAJOR; unsigned char min = HW_REV_MINOR; ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_MSB, &maj, 1); ok &= eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_LSB, &min, 1); putstr("\nset_hw_rev\n"); if (ok) printf("OK: set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR); else { printf("FAILED to set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR); hal_finish(); return 0; } if(test_sd()) puts("SD OK\n"); else { puts("SD FAIL\n"); //hal_finish(); //return 0; } if(test_ram()) puts("RAM OK\n"); else { puts("RAM FAIL\n"); hal_finish(); return 0; } print_mac_addr(ethernet_mac_addr()->addr); newline(); clocks_mimo_config(MC_WE_LOCK_TO_SMA); while (!clocks_lock_detect()) { puts("No Lock"); mdelay(1000); } puts("Clock Locked\n"); }
int main(void) { u2_init(); putstr("\nFactory Test\n"); print_mac_addr(ethernet_mac_addr()->addr); newline(); if(test_sd()) puts("SD OK\n"); else { puts("SD FAIL\n"); // hal_finish(); //return 0; } if(test_ram()) puts("RAM OK\n"); else { puts("RAM FAIL\n"); hal_finish(); return 0; } print_mac_addr(ethernet_mac_addr()->addr); newline(); output_regs->led_src = 0x7; // make bottom 3 controlled by HW ethernet_register_link_changed_callback(link_changed_callback); ethernet_init(); clocks_enable_tx_dboard(true,1); clocks_mimo_config(MC_WE_LOCK_TO_SMA); #if 0 // make bit 15 of Tx gpio's be a s/w output hal_gpio_set_sel(GPIO_TX_BANK, 15, 's'); hal_gpio_set_ddr(GPIO_TX_BANK, 0x8000, 0x8000); #endif output_regs->debug_mux_ctrl = 1; #if 0 hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111"); hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111"); hal_gpio_set_ddr(GPIO_TX_BANK, 0xffff, 0xffff); hal_gpio_set_ddr(GPIO_RX_BANK, 0xffff, 0xffff); #endif // initialize double buffering state machine for ethernet -> DSP Tx dbsm_init(&dsp_tx_sm, DSP_TX_BUF_0, &dsp_tx_recv_args, &dsp_tx_send_args, eth_pkt_inspector); // initialize double buffering state machine for DSP RX -> Ethernet if (FW_SETS_SEQNO){ dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, &dsp_rx_recv_args, &dsp_rx_send_args, fw_sets_seqno_inspector); } else { dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, &dsp_rx_recv_args, &dsp_rx_send_args, dbsm_nop_inspector); } // tell app_common that this dbsm could be sending to the ethernet ac_could_be_sending_to_eth = &dsp_rx_sm; // program tx registers setup_tx(); // kick off the state machine dbsm_start(&dsp_tx_sm); //int which = 0; while(1){ // hal_gpio_write(GPIO_TX_BANK, which, 0x8000); // which ^= 0x8000; buffer_irq_handler(0); int pending = pic_regs->pending; // poll for under or overrun if (pending & PIC_UNDERRUN_INT){ dbsm_handle_tx_underrun(&dsp_tx_sm); pic_regs->pending = PIC_UNDERRUN_INT; // clear interrupt putchar('U'); } if (pending & PIC_OVERRUN_INT){ dbsm_handle_rx_overrun(&dsp_rx_sm); pic_regs->pending = PIC_OVERRUN_INT; // clear pending interrupt // FIXME Figure out how to handle this robustly. // Any buffers that are emptying should be allowed to drain... if (streaming_p){ // restart_streaming(); // FIXME report error } else { // FIXME report error } putchar('O'); } } }