bool ide_wait( ide_device_info *device, int mask, int not_mask,
bool check_err, bigtime_t timeout )
{
ide_bus_info *bus = device->bus;
bigtime_t start_time = system_time();
while( 1 ) {
bigtime_t elapsed_time;
int status;
cpu_spin( 1 );
status = bus->controller->get_altstatus( bus->channel );
if( (status & mask) == mask &&
(status & not_mask) == 0 )
return true;
if( check_err && (status & ide_status_err) != 0 ) {
set_sense( device, SCSIS_KEY_HARDWARE_ERROR, SCSIS_ASC_INTERNAL_FAILURE );
return false;
}
elapsed_time = system_time() - start_time;
if( elapsed_time > timeout ) {
set_sense( device, SCSIS_KEY_HARDWARE_ERROR, SCSIS_ASC_LUN_TIMEOUT );
return false;
}
if( elapsed_time > 3000 )
thread_snooze( elapsed_time / 10 );
}
}
int xpt_flush_async( xpt_bus_info *bus )
{
// this is so rarely used that I don't want to add extra overhead
// to the service thread
while( bus->dpc_list )
thread_snooze( 10000 );
return NO_ERROR;
}
static void if_rx_thread(void *args)
{
ifnet *i = args;
cbuf *b;
t_current_set_name("IF Recv");
#if IF_PRIO
thread_set_priority(i->rx_thread, THREAD_MAX_RT_PRIORITY - 2);
#endif
//if(i->fd < 0) return -1;
for(;;) {
ssize_t len;
//len = sys_read(i->fd, i->rx_buf, 0, sizeof(i->rx_buf));
len = i->dev->dops.read(i->dev, i->rx_buf, sizeof(i->rx_buf));
#if 0||NET_CHATTY
dprintf("if_rx_thread: got ethernet packet, size %ld\n", (long)len);
#endif
if(len < 0) {
thread_snooze(10000);
continue;
}
if(len == 0)
continue;
#if LOSE_RX_PACKETS
if(rand() % 100 < LOSE_RX_PERCENTAGE) {
dprintf("if_rx_thread: purposely lost packet, size %d\n", len);
continue;
}
#endif
// check to see if we have a link layer address attached to us
if(!i->link_addr) {
#if 1||NET_CHATTY
dprintf("if_rx_thread: dumping packet because of no link address (%p)\n", i);
#endif
continue;
}
// for now just move it over into a cbuf
b = cbuf_get_chain(len);
if(!b) {
dprintf("if_rx_thread: could not allocate cbuf to hold ethernet packet\n");
continue;
}
cbuf_memcpy_to_chain(b, 0, i->rx_buf, len);
i->link_input(b, i);
}
}
static int if_rx_thread(void *args)
{
ifnet *i = args;
cbuf *b;
if(i->fd < 0)
return -1;
for(;;) {
ssize_t len;
len = sys_read(i->fd, i->rx_buf, 0, sizeof(i->rx_buf));
#if NET_CHATTY
dprintf("if_rx_thread: got ethernet packet, size %Ld\n", (long long)len);
#endif
if(len < 0) {
thread_snooze(10000);
continue;
}
if(len == 0)
continue;
#if LOSE_RX_PACKETS
if(rand() % 100 < LOSE_RX_PERCENTAGE) {
dprintf("if_rx_thread: purposely lost packet, size %d\n", len);
continue;
}
#endif
// check to see if we have a link layer address attached to us
if(!i->link_addr) {
#if NET_CHATTY
dprintf("if_rx_thread: dumping packet because of no link address (%p)\n", i);
#endif
continue;
}
// for now just move it over into a cbuf
b = cbuf_get_chain(len);
if(!b) {
dprintf("if_rx_thread: could not allocate cbuf to hold ethernet packet\n");
continue;
}
cbuf_memcpy_to_chain(b, 0, i->rx_buf, len);
i->link_input(b, i);
}
return 0;
}
int rhine_init(rhine *r)
{
bigtime_t time;
int err = -1;
addr_t temp;
int i;
dprintf("rhine_init: r %p\n", r);
r->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rhine_region", (void **)&r->virt_base,
REGION_ADDR_ANY_ADDRESS, r->phys_size, LOCK_KERNEL|LOCK_RW, r->phys_base);
if(r->region < 0) {
dprintf("rhine_init: error creating memory mapped region\n");
err = -1;
goto err;
}
dprintf("rhine mapped at address 0x%lx\n", r->virt_base);
/* create regions for tx and rx descriptors */
r->rxdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_rxdesc", (void **)&r->rxdesc,
REGION_ADDR_ANY_ADDRESS, RXDESC_COUNT * sizeof(struct rhine_rx_desc), REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->rxdesc_phys = vtophys(r->rxdesc);
dprintf("rhine: rx descriptors at %p, phys 0x%x\n", r->rxdesc, r->rxdesc_phys);
r->txdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_txdesc", (void **)&r->txdesc,
REGION_ADDR_ANY_ADDRESS, TXDESC_COUNT * sizeof(struct rhine_tx_desc), REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txdesc_phys = vtophys(r->txdesc);
dprintf("rhine: tx descriptors at %p, phys 0x%x\n", r->txdesc, r->txdesc_phys);
r->reg_spinlock = 0;
/* stick all rx and tx buffers in a circular buffer */
for (i=0; i < RXDESC_COUNT; i++) {
RXDESC(r, i).status = 0;
RXDESC(r, i).framelen = 0;
RXDESC(r, i).buflen = 0;
RXDESC(r, i).ptr = 0;
if (i == RXDESC_COUNT-1)
RXDESC(r, i).next = RXDESC_PHYS(r, 0);
else
RXDESC(r, i).next = RXDESC_PHYS(r, i + 1);
}
// XXX do same for tx
r->rx_head = r->rx_tail = 0;
/* reset the chip */
time = system_time();
RHINE_WRITE_16(r, RHINE_CR0, 0x8000); // reset the chip
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
break;
}
} while(RHINE_READ_16(r, RHINE_CR0) & 0x8000);
if (RHINE_READ_16(r, RHINE_CR0) & 0x8000) {
dprintf("chip didn't reset, trying alternate method\n");
RHINE_SETBITS_8(r, RHINE_MISC_CR1, 0x40);
thread_snooze(10000);
}
/* read in the mac address */
RHINE_WRITE_8(r, RHINE_EECSR, RHINE_READ_8(r, RHINE_EECSR) | (1<<5));
r->mac_addr[0] = RHINE_READ_8(r, RHINE_PAR0);
r->mac_addr[1] = RHINE_READ_8(r, RHINE_PAR1);
r->mac_addr[2] = RHINE_READ_8(r, RHINE_PAR2);
r->mac_addr[3] = RHINE_READ_8(r, RHINE_PAR3);
r->mac_addr[4] = RHINE_READ_8(r, RHINE_PAR4);
r->mac_addr[5] = RHINE_READ_8(r, RHINE_PAR5);
dprintf("rhine: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
/* set up the rx state */
/* 64 byte fifo threshold, all physical/broadcast/multicast/small/error packets accepted */
RHINE_WRITE_8(r, RHINE_RCR, (0<<5) | (1<<4) | (1<<3) | (1<<2) | (1<<1) | (1<<0));
RHINE_WRITE_32(r, RHINE_RDA0, RXDESC_PHYS(r, r->rx_head));
/* set up tx state */
/* 64 byte fifo, default backup, default loopback mode */
RHINE_WRITE_8(r, RHINE_TCR, 0);
/* mask all interrupts */
RHINE_WRITE_16(r, RHINE_IMR0, 0);
/* clear all pending interrupts */
RHINE_WRITE_16(r, RHINE_ISR0, 0xffff);
/* set up the interrupt handler */
int_set_io_interrupt_handler(r->irq, &rhine_int, r, "rhine");
{
static uint8 buf[2048];
RXDESC(r, r->rx_tail).ptr = vtophys(buf);
RXDESC(r, r->rx_tail).buflen = sizeof(buf);
RXDESC(r, r->rx_tail).status = 0;
RXDESC(r, r->rx_tail).framelen = RHINE_RX_OWNER;
r->rx_tail++;
RHINE_WRITE_16(r, RHINE_CR0, (1<<1) | (1<<3) | (1<<6));
}
/* unmask all interrupts */
RHINE_WRITE_16(r, RHINE_IMR0, 0xffff);
#if 0
// try to reset the device
time = system_time();
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RESET);
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
err = -1;
goto err1;
}
} while((RTL_READ_8(r, RT_CHIPCMD) & RT_CMD_RESET));
// create a rx and tx buf
r->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_rxbuf", (void **)&r->rxbuf,
REGION_ADDR_ANY_ADDRESS, 64*1024 + 16, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rhine_txbuf", (void **)&r->txbuf,
REGION_ADDR_ANY_ADDRESS, 8*1024, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
// set up the transmission buf and sem
r->tx_sem = sem_create(4, "rhine_txsem");
mutex_init(&r->lock, "rhine");
r->txbn = 0;
r->last_txbn = 0;
r->rx_sem = sem_create(0, "rhine_rxsem");
r->reg_spinlock = 0;
// set up the interrupt handler
int_set_io_interrupt_handler(r->irq, &rhine_int, r, "rhine");
// read the mac address
r->mac_addr[0] = RTL_READ_8(r, RT_IDR0);
r->mac_addr[1] = RTL_READ_8(r, RT_IDR0 + 1);
r->mac_addr[2] = RTL_READ_8(r, RT_IDR0 + 2);
r->mac_addr[3] = RTL_READ_8(r, RT_IDR0 + 3);
r->mac_addr[4] = RTL_READ_8(r, RT_IDR0 + 4);
r->mac_addr[5] = RTL_READ_8(r, RT_IDR0 + 5);
dprintf("rhine: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
// enable writing to the config registers
RTL_WRITE_8(r, RT_CFG9346, 0xc0);
// reset config 1
RTL_WRITE_8(r, RT_CONFIG1, 0);
// Enable receive and transmit functions
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
// Set Rx FIFO threashold to 256, Rx size to 64k+16, 256 byte DMA burst
RTL_WRITE_32(r, RT_RXCONFIG, 0x00009c00);
// Set Tx 256 byte DMA burst
RTL_WRITE_32(r, RT_TXCONFIG, 0x03000400);
// Turn off lan-wake and set the driver-loaded bit
RTL_WRITE_8(r, RT_CONFIG1, (RTL_READ_8(r, RT_CONFIG1) & ~0x30) | 0x20);
// Enable FIFO auto-clear
RTL_WRITE_8(r, RT_CONFIG4, RTL_READ_8(r, RT_CONFIG4) | 0x80);
// go back to normal mode
RTL_WRITE_8(r, RT_CFG9346, 0);
// Setup RX buffers
*(int *)r->rxbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->rxbuf, &temp);
dprintf("rx buffer will be at 0x%lx\n", temp);
RTL_WRITE_32(r, RT_RXBUF, temp);
// Setup TX buffers
dprintf("tx buffer (virtual) is at 0x%lx\n", r->txbuf);
*(int *)r->txbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->txbuf, &temp);
RTL_WRITE_32(r, RT_TXADDR0, temp);
RTL_WRITE_32(r, RT_TXADDR1, temp + 2*1024);
dprintf("first half of txbuf at 0x%lx\n", temp);
*(int *)(r->txbuf + 4*1024) = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), r->txbuf + 4*1024, &temp);
RTL_WRITE_32(r, RT_TXADDR2, temp);
RTL_WRITE_32(r, RT_TXADDR3, temp + 2*1024);
dprintf("second half of txbuf at 0x%lx\n", temp);
/*
RTL_WRITE_32(r, RT_TXSTATUS0, RTL_READ_32(r, RT_TXSTATUS0) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS1, RTL_READ_32(r, RT_TXSTATUS1) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS2, RTL_READ_32(r, RT_TXSTATUS2) | 0xfffff000);
RTL_WRITE_32(r, RT_TXSTATUS3, RTL_READ_32(r, RT_TXSTATUS3) | 0xfffff000);
*/
// Reset RXMISSED counter
RTL_WRITE_32(r, RT_RXMISSED, 0);
// Enable receiving broadcast and physical match packets
// RTL_WRITE_32(r, RT_RXCONFIG, RTL_READ_32(r, RT_RXCONFIG) | 0x0000000a);
RTL_WRITE_32(r, RT_RXCONFIG, RTL_READ_32(r, RT_RXCONFIG) | 0x0000000f);
// Filter out all multicast packets
RTL_WRITE_32(r, RT_MAR0, 0);
RTL_WRITE_32(r, RT_MAR0 + 4, 0);
// Disable all multi-interrupts
RTL_WRITE_16(r, RT_MULTIINTR, 0);
RTL_WRITE_16(r, RT_INTRMASK, MYRT_INTS);
// RTL_WRITE_16(r, RT_INTRMASK, 0x807f);
// Enable RX/TX once more
RTL_WRITE_8(r, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
RTL_WRITE_8(r, RT_CFG9346, 0);
#endif
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), r->region);
err:
return err;
}
int rtl8169_init(rtl8169 *r)
{
bigtime_t time;
int err = -1;
addr_t temp;
int i;
SHOW_FLOW(2, "rtl8169_init: r %p\n", r);
r->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rtl8169_region", (void **)&r->virt_base,
REGION_ADDR_ANY_ADDRESS, r->phys_size, LOCK_KERNEL|LOCK_RW, r->phys_base);
if(r->region < 0) {
SHOW_ERROR0(1, "rtl8169_init: error creating memory mapped region\n");
err = -1;
goto err;
}
SHOW_INFO(2, "rtl8169 mapped at address 0x%lx\n", r->virt_base);
/* create regions for tx and rx descriptors */
r->rxdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_rxdesc", (void **)&r->rxdesc,
REGION_ADDR_ANY_ADDRESS, NUM_RX_DESCRIPTORS * DESCRIPTOR_LEN, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->rxdesc_phys = vtophys(r->rxdesc);
SHOW_INFO(2, "rtl8169: rx descriptors at %p, phys 0x%x\n", r->rxdesc, r->rxdesc_phys);
r->txdesc_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_txdesc", (void **)&r->txdesc,
REGION_ADDR_ANY_ADDRESS, NUM_TX_DESCRIPTORS * DESCRIPTOR_LEN, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
r->txdesc_phys = vtophys(r->txdesc);
SHOW_INFO(2, "rtl8169: tx descriptors at %p, phys 0x%x\n", r->txdesc, r->txdesc_phys);
r->reg_spinlock = 0;
/* create a large tx and rx buffer for the descriptors to point to */
r->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_rxbuf", (void **)&r->rxbuf,
REGION_ADDR_ANY_ADDRESS, NUM_RX_DESCRIPTORS * BUFSIZE_PER_FRAME, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
r->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8169_txbuf", (void **)&r->txbuf,
REGION_ADDR_ANY_ADDRESS, NUM_TX_DESCRIPTORS * BUFSIZE_PER_FRAME, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
/* create a receive sem */
r->rx_sem = sem_create(0, "rtl8169 rx_sem");
/* transmit sem */
r->tx_sem = sem_create(1, "rtl8169 tx_sem");
/* reset the chip */
time = system_time();
RTL_WRITE_8(r, REG_CR, (1<<4)); // reset the chip, disable tx/rx
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
break;
}
} while(RTL_READ_8(r, REG_CR) & (1<<4));
/* read in the mac address */
r->mac_addr[0] = RTL_READ_8(r, REG_IDR0);
r->mac_addr[1] = RTL_READ_8(r, REG_IDR1);
r->mac_addr[2] = RTL_READ_8(r, REG_IDR2);
r->mac_addr[3] = RTL_READ_8(r, REG_IDR3);
r->mac_addr[4] = RTL_READ_8(r, REG_IDR4);
r->mac_addr[5] = RTL_READ_8(r, REG_IDR5);
SHOW_INFO(2, "rtl8169: mac addr %x:%x:%x:%x:%x:%x\n",
r->mac_addr[0], r->mac_addr[1], r->mac_addr[2],
r->mac_addr[3], r->mac_addr[4], r->mac_addr[5]);
/* some voodoo from BSD driver */
RTL_WRITE_16(r, REG_CCR, RTL_READ_16(r, REG_CCR));
RTL_SETBITS_16(r, REG_CCR, 0x3);
/* mask all interrupts */
RTL_WRITE_16(r, REG_IMR, 0);
/* set up the tx/rx descriptors */
rtl8169_setup_descriptors(r);
/* enable tx/rx */
RTL_SETBITS_8(r, REG_CR, (1<<3)|(1<<2));
/* set up the rx state */
/* 1024 byte dma threshold, 1024 dma max burst, CRC calc 8 byte+, accept all packets */
RTL_WRITE_32(r, REG_RCR, (1<<16) | (6<<13) | (6<<8) | (0xf << 0));
RTL_SETBITS_16(r, REG_CCR, (1<<5)); // rx checksum enable
RTL_WRITE_16(r, REG_RMS, 1518); // rx mtu
/* set up the tx state */
RTL_WRITE_32(r, REG_TCR, (RTL_READ_32(r, REG_TCR) & ~0x1ff) | (6<<8)); // 1024 max burst dma
RTL_WRITE_8(r, REG_MTPS, 0x3f); // max tx packet size (must be careful to not actually transmit more than mtu)
/* set up the interrupt handler */
int_set_io_interrupt_handler(r->irq, &rtl8169_int, r, "rtl8169");
/* clear all pending interrupts */
RTL_WRITE_16(r, REG_ISR, 0xffff);
/* unmask interesting interrupts */
RTL_WRITE_16(r, REG_IMR, IMR_SYSERR | IMR_LINKCHG | IMR_TER | IMR_TOK | IMR_RER | IMR_ROK | IMR_RXOVL);
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), r->region);
err:
return err;
}
int rtl8139_init(rtl8139 *rtl)
{
bigtime_t time;
int err = -1;
addr_t temp;
dprintf("rtl8139_init: rtl %p\n", rtl);
rtl->region = vm_map_physical_memory(vm_get_kernel_aspace_id(), "rtl8139_region", (void **)&rtl->virt_base,
REGION_ADDR_ANY_ADDRESS, rtl->phys_size, LOCK_KERNEL|LOCK_RW, rtl->phys_base);
if(rtl->region < 0) {
dprintf("rtl8139_init: error creating memory mapped region\n");
err = -1;
goto err;
}
dprintf("rtl8139 mapped at address 0x%lx\n", rtl->virt_base);
// try to reset the device
time = system_time();
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RESET);
do {
thread_snooze(10000); // 10ms
if(system_time() - time > 1000000) {
err = -1;
goto err1;
}
} while((RTL_READ_8(rtl, RT_CHIPCMD) & RT_CMD_RESET));
// create a rx and tx buf
rtl->rxbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8139_rxbuf", (void **)&rtl->rxbuf,
REGION_ADDR_ANY_ADDRESS, 64*1024 + 16, REGION_WIRING_WIRED_CONTIG, LOCK_KERNEL|LOCK_RW);
rtl->txbuf_region = vm_create_anonymous_region(vm_get_kernel_aspace_id(), "rtl8139_txbuf", (void **)&rtl->txbuf,
REGION_ADDR_ANY_ADDRESS, 8*1024, REGION_WIRING_WIRED, LOCK_KERNEL|LOCK_RW);
// set up the transmission buf and sem
rtl->tx_sem = sem_create(4, "rtl8139_txsem");
mutex_init(&rtl->lock, "rtl8139");
rtl->txbn = 0;
rtl->last_txbn = 0;
rtl->rx_sem = sem_create(0, "rtl8139_rxsem");
rtl->reg_spinlock = 0;
// set up the interrupt handler
int_set_io_interrupt_handler(rtl->irq, &rtl8139_int, rtl, "rtl8139");
// read the mac address
rtl->mac_addr[0] = RTL_READ_8(rtl, RT_IDR0);
rtl->mac_addr[1] = RTL_READ_8(rtl, RT_IDR0 + 1);
rtl->mac_addr[2] = RTL_READ_8(rtl, RT_IDR0 + 2);
rtl->mac_addr[3] = RTL_READ_8(rtl, RT_IDR0 + 3);
rtl->mac_addr[4] = RTL_READ_8(rtl, RT_IDR0 + 4);
rtl->mac_addr[5] = RTL_READ_8(rtl, RT_IDR0 + 5);
dprintf("rtl8139: mac addr %x:%x:%x:%x:%x:%x\n",
rtl->mac_addr[0], rtl->mac_addr[1], rtl->mac_addr[2],
rtl->mac_addr[3], rtl->mac_addr[4], rtl->mac_addr[5]);
// enable writing to the config registers
RTL_WRITE_8(rtl, RT_CFG9346, 0xc0);
// reset config 1
RTL_WRITE_8(rtl, RT_CONFIG1, 0);
// Enable receive and transmit functions
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
// Set Rx FIFO threashold to 256, Rx size to 64k+16, 256 byte DMA burst
RTL_WRITE_32(rtl, RT_RXCONFIG, 0x00009c00);
// Set Tx 256 byte DMA burst
RTL_WRITE_32(rtl, RT_TXCONFIG, 0x03000400);
// Turn off lan-wake and set the driver-loaded bit
RTL_WRITE_8(rtl, RT_CONFIG1, (RTL_READ_8(rtl, RT_CONFIG1) & ~0x30) | 0x20);
// Enable FIFO auto-clear
RTL_WRITE_8(rtl, RT_CONFIG4, RTL_READ_8(rtl, RT_CONFIG4) | 0x80);
// go back to normal mode
RTL_WRITE_8(rtl, RT_CFG9346, 0);
// Setup RX buffers
*(int *)rtl->rxbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->rxbuf, &temp);
dprintf("rx buffer will be at 0x%lx\n", temp);
RTL_WRITE_32(rtl, RT_RXBUF, temp);
// Setup TX buffers
dprintf("tx buffer (virtual) is at 0x%lx\n", rtl->txbuf);
*(int *)rtl->txbuf = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->txbuf, &temp);
RTL_WRITE_32(rtl, RT_TXADDR0, temp);
RTL_WRITE_32(rtl, RT_TXADDR1, temp + 2*1024);
dprintf("first half of txbuf at 0x%lx\n", temp);
*(int *)(rtl->txbuf + 4*1024) = 0;
vm_get_page_mapping(vm_get_kernel_aspace_id(), rtl->txbuf + 4*1024, &temp);
RTL_WRITE_32(rtl, RT_TXADDR2, temp);
RTL_WRITE_32(rtl, RT_TXADDR3, temp + 2*1024);
dprintf("second half of txbuf at 0x%lx\n", temp);
/*
RTL_WRITE_32(rtl, RT_TXSTATUS0, RTL_READ_32(rtl, RT_TXSTATUS0) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS1, RTL_READ_32(rtl, RT_TXSTATUS1) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS2, RTL_READ_32(rtl, RT_TXSTATUS2) | 0xfffff000);
RTL_WRITE_32(rtl, RT_TXSTATUS3, RTL_READ_32(rtl, RT_TXSTATUS3) | 0xfffff000);
*/
// Reset RXMISSED counter
RTL_WRITE_32(rtl, RT_RXMISSED, 0);
// Enable receiving broadcast and physical match packets
// RTL_WRITE_32(rtl, RT_RXCONFIG, RTL_READ_32(rtl, RT_RXCONFIG) | 0x0000000a);
RTL_WRITE_32(rtl, RT_RXCONFIG, RTL_READ_32(rtl, RT_RXCONFIG) | 0x0000000f);
// Filter out all multicast packets
RTL_WRITE_32(rtl, RT_MAR0, 0);
RTL_WRITE_32(rtl, RT_MAR0 + 4, 0);
// Disable all multi-interrupts
RTL_WRITE_16(rtl, RT_MULTIINTR, 0);
RTL_WRITE_16(rtl, RT_INTRMASK, MYRT_INTS);
// RTL_WRITE_16(rtl, RT_INTRMASK, 0x807f);
// Enable RX/TX once more
RTL_WRITE_8(rtl, RT_CHIPCMD, RT_CMD_RX_ENABLE | RT_CMD_TX_ENABLE);
RTL_WRITE_8(rtl, RT_CFG9346, 0);
return 0;
err1:
vm_delete_region(vm_get_kernel_aspace_id(), rtl->region);
err:
return err;
}
// we need a device to store sense information
// (we could just take device 0, but this were not fair if the reset
// was done because of a device 1 failure)
bool reset_bus( ide_device_info *device )
{
ide_bus_info *bus = device->bus;
ide_controller_interface *controller = bus->controller;
ide_channel_cookie channel = bus->channel;
SHOW_FLOW0( 3, "" );
// activate srst signal for 5 µs
reset_timeouts( device );
reset_timeouts( device->other_device );
//set_irq_state( device, ide_irq_state_ignore );
SHOW_FLOW0( 3, "1" );
if( controller->write_device_control( channel,
ide_devctrl_nien | ide_devctrl_srst | ide_devctrl_bit3 ) != NO_ERROR )
goto err0;
SHOW_FLOW0( 3, "2" );
cpu_spin( 5 );
if( controller->write_device_control( channel,
ide_devctrl_nien | ide_devctrl_bit3 ) != NO_ERROR )
goto err0;
SHOW_FLOW0( 3, "3" );
// let devices wake up
thread_snooze( 2000 );
SHOW_FLOW0( 3, "4" );
// ouch, we have to wait up to 31 seconds!
if( !ide_wait( device, 0, ide_status_bsy, false, 31000000 )) {
// we don't know which of the devices is broken
// so we don't disable them
if( controller->write_device_control( channel, ide_devctrl_bit3 ) != NO_ERROR )
goto err0;
set_sense( device, SCSIS_KEY_HARDWARE_ERROR, SCSIS_ASC_LUN_TIMEOUT );
goto err1;
}
SHOW_FLOW0( 3, "5" );
if( controller->write_device_control( channel, ide_devctrl_bit3 ) != NO_ERROR )
goto err0;
SHOW_FLOW0( 3, "6" );
finish_all_requests( bus->devices[0], CAM_SCSI_BUS_RESET );
finish_all_requests( bus->devices[1], CAM_SCSI_BUS_RESET );
SHOW_FLOW0( 3, "7" );
xpt->call_async( bus->xpt_cookie, -1, -1, AC_BUS_RESET, NULL, 0 );
SHOW_FLOW0( 3, "8" );
return true;
err0:
set_sense( device, SCSIS_KEY_HARDWARE_ERROR, SCSIS_ASC_INTERNAL_FAILURE );
err1:
finish_all_requests( bus->devices[0], CAM_SCSI_BUS_RESET );
finish_all_requests( bus->devices[1], CAM_SCSI_BUS_RESET );
xpt->call_async( bus->xpt_cookie, -1, -1, AC_BUS_RESET, NULL, 0 );
return false;
}
