static void tim_setup()
{
//Some explanation: HCLK=72MHz
//APB1-Prescaler is 2 -> 36MHz
//Timer clock source is ABP1*2 because APB1 prescaler > 1
//So clock source is 72MHz (again)
//We want the timer to run at 1MHz = 72MHz/72
//Prescaler is div-1 => 71
timer_set_prescaler(REV_CNT_TIMER, 71);
timer_set_period(REV_CNT_TIMER, MAX_CNT);
timer_update_on_overflow(REV_CNT_TIMER);
timer_direction_up(REV_CNT_TIMER);
/*timer_ic_enable(REV_CNT_TIMER, REV_CNT_IC);
timer_ic_set_filter(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_DTF_DIV_32_N_6);
timer_ic_set_prescaler(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_PSC_OFF);
timer_ic_set_input(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_IN_TI2);*/
/* Reset counter on input pulse. Filter constant must be larger than that of the capture input
So that the counter value is first saved, then reset */
TIM_SMCR(REV_CNT_TIMER) = TIM_SMCR_SMS_RM | TIM_SMCR_TS_ETRF | TIM_SMCR_ETP | TIM_SMCR_ETF_DTS_DIV_32_N_8;
/* Save timer value on input pulse with smaller filter constant */
TIM_CCMR2(REV_CNT_TIMER) = REV_CNT_CCMR2 | TIM_CCMR2_IC3F_DTF_DIV_32_N_6;
TIM_CCER(REV_CNT_TIMER) |= REV_CNT_CCER; //1 << (1 + 4 * REV_CNT_IC);
//timer_enable_irq(REV_CNT_TIMER, TIM_DIER_CC3IE);
//timer_set_dma_on_compare_event(REV_CNT_TIMER);
timer_generate_event(REV_CNT_TIMER, TIM_EGR_UG);
timer_enable_counter(REV_CNT_TIMER);
}
// init common timer
// use SOFTI2C_TIMER_1 timer
void delay_timer_init() {
rcc_periph_clock_enable(get_rcc_by_port(SOFTI2C_TIMER_1));
timer_set_prescaler(SOFTI2C_TIMER_1, 72);
timer_direction_up(SOFTI2C_TIMER_1);
timer_continuous_mode(SOFTI2C_TIMER_1);
timer_set_counter(SOFTI2C_TIMER_1, 0);
/* Start timer. */
TIM_CR1(SOFTI2C_TIMER_1) |= TIM_CR1_CEN;
timer_enable_counter(SOFTI2C_TIMER_1);
}
