static void tim_setup() { //Some explanation: HCLK=72MHz //APB1-Prescaler is 2 -> 36MHz //Timer clock source is ABP1*2 because APB1 prescaler > 1 //So clock source is 72MHz (again) //We want the timer to run at 1MHz = 72MHz/72 //Prescaler is div-1 => 71 timer_set_prescaler(REV_CNT_TIMER, 71); timer_set_period(REV_CNT_TIMER, MAX_CNT); timer_update_on_overflow(REV_CNT_TIMER); timer_direction_up(REV_CNT_TIMER); /*timer_ic_enable(REV_CNT_TIMER, REV_CNT_IC); timer_ic_set_filter(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_DTF_DIV_32_N_6); timer_ic_set_prescaler(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_PSC_OFF); timer_ic_set_input(REV_CNT_TIMER, REV_CNT_IC, TIM_IC_IN_TI2);*/ /* Reset counter on input pulse. Filter constant must be larger than that of the capture input So that the counter value is first saved, then reset */ TIM_SMCR(REV_CNT_TIMER) = TIM_SMCR_SMS_RM | TIM_SMCR_TS_ETRF | TIM_SMCR_ETP | TIM_SMCR_ETF_DTS_DIV_32_N_8; /* Save timer value on input pulse with smaller filter constant */ TIM_CCMR2(REV_CNT_TIMER) = REV_CNT_CCMR2 | TIM_CCMR2_IC3F_DTF_DIV_32_N_6; TIM_CCER(REV_CNT_TIMER) |= REV_CNT_CCER; //1 << (1 + 4 * REV_CNT_IC); //timer_enable_irq(REV_CNT_TIMER, TIM_DIER_CC3IE); //timer_set_dma_on_compare_event(REV_CNT_TIMER); timer_generate_event(REV_CNT_TIMER, TIM_EGR_UG); timer_enable_counter(REV_CNT_TIMER); }
void BeepInit(void) { rcc_peripheral_enable_clock(&RCC_APB1ENR, BEEP_RCC_APB1ENR_TIMEN); gpio_set_mode(BEEP_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, BEEP_PIN); timer_set_mode(BEEP_TIM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Period */ timer_set_period(BEEP_TIM, 65535); /* Prescaler */ timer_set_prescaler(BEEP_TIM, 5); timer_generate_event(BEEP_TIM, TIM_EGR_UG); /* ---- */ /* Output compare 1 mode and preload */ timer_set_oc_mode(BEEP_TIM, BEEP_TIM_OC, TIM_OCM_PWM1); timer_enable_oc_preload(BEEP_TIM, BEEP_TIM_OC); /* Polarity and state */ timer_set_oc_polarity_low(BEEP_TIM, BEEP_TIM_OC); timer_enable_oc_output(BEEP_TIM, BEEP_TIM_OC); /* Capture compare value */ timer_set_oc_value(BEEP_TIM, BEEP_TIM_OC, 0x8000); /* ---- */ /* ARR reload enable */ timer_enable_preload(BEEP_TIM); }
/** * Timer 2 interrupt handler */ void tim2_isr(void) { if (timer_get_flag(TIM2, TIM_SR_CC1IF)) { timer_clear_flag(TIM2, TIM_SR_CC1IF); /* prepare for next comm */ comm_tim_data.last_capture_time = timer_get_counter(TIM2); //comm_tim_data.last_capture_time = timer_get_ic_value(TIM2, TIM_OC1); //comm_tim_data.last_capture_time = TIM2_CCR1; /* triggering commutation event */ if (comm_tim_trigger_comm || comm_tim_trigger_comm_once) { timer_generate_event(TIM1, TIM_EGR_COMG); //timer_generate_event(TIM1, TIM_EGR_COMG | TIM_EGR_UG); } /* (re)setting "semaphors" */ comm_tim_trigger_comm_once = false; comm_tim_trigger = true; /* Set next comm time */ timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.last_capture_time + (comm_tim_data.freq * 2)); //timer_set_oc_value(TIM2, TIM_OC1, // comm_tim_data.last_capture_time + // 65535); TOGGLE(DP_EXT_SCL); } if (timer_get_flag(TIM2, TIM_SR_UIF)) { timer_clear_flag(TIM2, TIM_SR_UIF); comm_tim_state.update_count++; } }
void BACKLIGHT_Init() { rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); //Turn off backlight gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); //Configure Backlight PWM rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(TIM3, 0x2CF); timer_set_prescaler(TIM3, 0); timer_generate_event(TIM3, TIM_EGR_UG); //timer_set_repetition_counter(TIM3, 0); timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); timer_enable_oc_preload(TIM3, TIM_OC4); timer_set_oc_polarity_high(TIM3, TIM_OC4); timer_enable_oc_output(TIM3, TIM_OC4); timer_enable_preload(TIM3); }
void PID_tim_init(void) { /* Enable TIM1 clock. and Port E clock (for outputs) */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //Set TIM1 channel (and complementary) output to alternate function push-pull'. //f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3 //f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13); gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13); gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12); gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12); /* Enable TIM1 commutation interrupt. */ //nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4 /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now. TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE //TIM_CR1_CMS_CENTER_1 //TIM_CR1_CMS_CENTER_2 //TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal) TIM_CR1_DIR_UP); timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed) timer_set_repetition_counter(TIM1, 0); //disabled timer_enable_preload(TIM1); timer_continuous_mode(TIM1); /* Period (32kHz). */ timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter) /* Configure break and deadtime. */ //timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR); timer_set_enabled_off_state_in_idle_mode(TIM1); timer_set_enabled_off_state_in_run_mode(TIM1); timer_disable_break(TIM1); timer_set_break_polarity_high(TIM1); timer_disable_break_automatic_output(TIM1); timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC1N); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC2N); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC3N); /* -- OC1 and OC1N configuration -- */ /* Configure global mode of line 1. */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); /* Configure OC1. */ timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output /* Configure OC1N. */ timer_set_oc_polarity_high(TIM1, TIM_OC1N); timer_set_oc_idle_state_unset(TIM1, TIM_OC1N); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC2 and OC2N configuration -- */ /* Configure global mode of line 2. */ timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); /* Configure OC2. */ timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_idle_state_unset(TIM1, TIM_OC2); /* Configure OC2N. */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); timer_set_oc_idle_state_unset(TIM1, TIM_OC2N); /* Set the capture compare value for OC2. */ timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC3 and OC3N configuration -- */ /* Configure global mode of line 3. */ timer_enable_oc_preload(TIM1, TIM_OC3); timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); /* Configure OC3. */ timer_set_oc_polarity_high(TIM1, TIM_OC3); timer_set_oc_idle_state_unset(TIM1, TIM_OC3); /* Configure OC3N. */ timer_set_oc_polarity_high(TIM1, TIM_OC3N); timer_set_oc_idle_state_unset(TIM1, TIM_OC3N); /* Set the capture compare value for OC3. */ timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100); /* Reenable outputs. */ timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC3); timer_enable_oc_output(TIM1, TIM_OC3N); /* ---- */ /* ARR reload enable. */ timer_enable_preload(TIM1); /* * Enable preload of complementary channel configurations and * update on COM event. */ //timer_enable_preload_complementry_enable_bits(TIM1); timer_disable_preload_complementry_enable_bits(TIM1); /* Enable outputs in the break subsystem. */ timer_enable_break_main_output(TIM1); /* Generate update event to reload all registers before starting*/ timer_generate_event(TIM1, TIM_EGR_UG); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_COMIE); /*********/ /*Capture compare interrupt*/ //enable capture compare interrupt timer_enable_update_event(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); }
void hardware_setup(void) { /* Set the clock to 72MHz from the 8MHz external crystal */ rcc_clock_setup_in_hse_8mhz_out_72mhz(); /* Enable GPIOA, GPIOB and GPIOC clocks. APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR) Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN for Alternate Function clock */ rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_AFIO); /* Set ports PA8 (TIM1_CH1), PA9 (TIM1_CH2), PB13 (TIM1_CH1N), PB14 (TIM1_CH2N) for PWM, to 'alternate function output push-pull'. */ gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8 | GPIO9); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO14); /* ------------------ Timer 1 PWM */ /* Enable TIM1 clock. */ rcc_periph_clock_enable(RCC_TIM1); /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Set Timer global mode: * - No division * - Alignment centre mode 1 (up/down counting, interrupt on downcount only) * - Direction up (when centre mode is set it is read only, changes by hardware) */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); /* Set Timer output compare mode: * - Channel 1 * - PWM mode 2 (output low when CNT < CCR1, high otherwise) */ timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_break_main_output(TIM1); /* Set the polarity of OCN to be high to match that of the OC, for switching the low MOSFET through an inverting level shifter */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); /* The ARR (auto-preload register) sets the PWM period to 62.5kHz from the 72 MHz clock.*/ timer_enable_preload(TIM1); timer_set_period(TIM1, PERIOD); /* The CCR1 (capture/compare register 1) sets the PWM duty cycle to default 50% */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_value(TIM1, TIM_OC1, (PERIOD*20)/100); timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_value(TIM1, TIM_OC2, (PERIOD*50)/100); /* Force an update to load the shadow registers */ timer_generate_event(TIM1, TIM_EGR_UG); /* Start the Counter. */ timer_enable_counter(TIM1); }