/** Configure and enable RCC for peripherals (ADC1, ADC2, Timer) */ static inline void adc_init_rcc( void ) { #if USE_AD1 || USE_AD2 || USE_AD3 /* Timer peripheral clock enable. */ rcc_periph_clock_enable(RCC_TIM_ADC); #if defined(STM32F4) adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2); #endif /* Enable ADC peripheral clocks. */ #if USE_AD1 rcc_periph_clock_enable(RCC_ADC1); #endif #if USE_AD2 rcc_periph_clock_enable(RCC_ADC2); #endif #if USE_AD3 rcc_periph_clock_enable(RCC_ADC3); #endif /* Time Base configuration */ timer_reset(TIM_ADC); timer_set_mode(TIM_ADC, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* timer counts with ADC_TIMER_FREQUENCY */ uint32_t timer_clk = timer_get_frequency(TIM_ADC); timer_set_prescaler(TIM_ADC, (timer_clk / ADC_TIMER_FREQUENCY) - 1); timer_set_period(TIM_ADC, ADC_TIMER_PERIOD); /* Generate TRGO on every update (when counter reaches period reload value) */ timer_set_master_mode(TIM_ADC, TIM_CR2_MMS_UPDATE); timer_enable_counter(TIM_ADC); #endif // USE_AD1 || USE_AD2 || USE_AD3 }
static inline void pwm_input_set_timer(uint32_t tim, uint32_t ticks_per_usec) { timer_reset(tim); timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(tim, 0xFFFF); uint32_t timer_clk = timer_get_frequency(tim); timer_set_prescaler(tim, (timer_clk / (ticks_per_usec * ONE_MHZ_CLK)) - 1); timer_enable_counter(tim); }
/** Set Timer configuration * @param[in] timer Timer register address base * @param[in] period period in us * @param[in] channels_mask output compare channels to enable */ void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) { // WARNING, this reset is only implemented for TIM1-8 in libopencm3!! timer_reset(timer); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ if ((timer == TIM9) || (timer == TIM12)) //There are no EDGE and DIR settings in TIM9 and TIM12 timer_set_mode(timer, TIM_CR1_CKD_CK_INT, 0, 0); else timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // By default the PWM_BASE_FREQ is set to 1MHz thus the timer tick period is 1uS uint32_t timer_clk = timer_get_frequency(timer); timer_set_prescaler(timer, (timer_clk / PWM_BASE_FREQ) -1); timer_disable_preload(timer); timer_continuous_mode(timer); timer_set_period(timer, (PWM_BASE_FREQ / period) - 1); /* Disable outputs and configure channel if needed. */ if (bit_is_set(channels_mask, 0)) { actuators_pwm_arch_channel_init(timer, TIM_OC1); } if (bit_is_set(channels_mask, 1)) { actuators_pwm_arch_channel_init(timer, TIM_OC2); } if (bit_is_set(channels_mask, 2)) { actuators_pwm_arch_channel_init(timer, TIM_OC3); } if (bit_is_set(channels_mask, 3)) { actuators_pwm_arch_channel_init(timer, TIM_OC4); } /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(timer, TIM_OC1, 1000); //timer_set_oc_value(timer, TIM_OC2, 1000); //timer_set_oc_value(timer, TIM_OC3, 1000); //timer_set_oc_value(timer, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(timer); /* Counter enable. */ timer_enable_counter(timer); }