static void gpt_irq_acknowledge(void)
{
if (timer_is_v1()) {
if (cpu_is_mx1())
__raw_writel(0, timer_base + MX1_2_TSTAT);
else
__raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
timer_base + MX1_2_TSTAT);
} else if (timer_is_v2())
__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}
void __init
mxc_timer_init(struct clk *timer_clk,
void __iomem *base, unsigned long phys, int irq)
{
uint32_t tctl_val;
clk_enable(timer_clk);
timer_base = base;
/*
* Initialise to a known state (all timers off, and timing reset)
*/
__raw_writel(0, timer_base + MXC_TCTL);
__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
if (timer_is_v2())
tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
else
tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
__raw_writel(tctl_val, timer_base + MXC_TCTL);
/* init and register the timer to the framework */
mxc_clocksource_init(timer_clk);
mxc_clockevent_init(timer_clk);
/* Make irqs happen */
setup_irq(irq, &mxc_timer_irq);
#ifdef CONFIG_IPIPE
__ipipe_mach_timerint = irq;
__ipipe_mach_ticks_per_jiffy = (clk_get_rate(timer_clk) + HZ/2) / HZ;
tsc_info.freq = clk_get_rate(timer_clk);
mxc_min_delay = ((__ipipe_cpu_freq + 500000) / 1000000) ?: 1;
if (timer_is_v1()) {
tsc_info.u.counter_paddr = phys + MX1_2_TCN;
tsc_info.counter_vaddr =(unsigned long)(phys + MX1_2_TCN);
} else {
tsc_info.u.counter_paddr = phys + V2_TCN;
tsc_info.counter_vaddr = (unsigned long)(timer_base + V2_TCN);
}
__ipipe_tsc_register(&tsc_info);
#endif /* CONFIG_IPIPE */
}