void LED_init(void) { rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); set_led(false); timer_reset(TIM2); timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM2, 256); timer_enable_preload(TIM2); timer_one_shot_mode(TIM2); timer_set_period(TIM2, (uint16_t)((rcc_ppre1_frequency/256) / 20)); timer_enable_irq(TIM2, TIM_DIER_UIE); timer_clear_flag(TIM2, TIM_SR_UIF); nvic_enable_irq(NVIC_TIM2_IRQ); nvic_set_priority(NVIC_TIM2_IRQ, 128); }
void baro_init() { gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO14); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO13 | GPIO15); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO12); deselect_slave(); spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_8, SPI_CR1_CPOL, SPI_CR1_CPHA, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST); spi_enable_ss_output(SPI2); spi_enable(SPI2); dma_set_peripheral_address(DMA1, DMA_CHANNEL3, SPI2_DR); dma_set_read_from_memory(DMA1, DMA_CHANNEL3); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3); dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH); dma_set_peripheral_address(DMA1, DMA_CHANNEL4, SPI2_DR); dma_set_read_from_peripheral(DMA1, DMA_CHANNEL4); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL4); dma_set_peripheral_size(DMA1, DMA_CHANNEL4, DMA_CCR_PSIZE_8BIT); dma_set_memory_size(DMA1, DMA_CHANNEL4, DMA_CCR_MSIZE_8BIT); dma_set_priority(DMA1, DMA_CHANNEL4, DMA_CCR_PL_VERY_HIGH); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL4); timer_reset(TIM4); timer_enable_irq(TIM4, TIM_DIER_UIE); timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 3200 / 16 = 200 Hz */ timer_set_prescaler(TIM4, 32); timer_set_period(TIM4, 5625); nvic_set_priority(NVIC_TIM4_IRQ, 16 * 2); nvic_set_priority(NVIC_DMA1_CHANNEL4_IRQ, 16 * 2); nvic_enable_irq(NVIC_TIM4_IRQ); nvic_enable_irq(NVIC_DMA1_CHANNEL4_IRQ); read_calibration_data(); }
void buzzer_nonblocking_buzz(float time) { buzz_time = 4100*time*2; // Configure timer2 to fire every N microseconds timer_pause(TIMER2); timer_set_prescaler(TIMER2,1); timer_set_reload(TIMER2,(125*CYCLES_PER_MICROSECOND)/2); // setup interrupt on channel 2 timer_set_mode(TIMER2,TIMER_CH2,TIMER_OUTPUT_COMPARE); timer_set_compare(TIMER2,TIMER_CH2,MAX_RELOAD-1); timer_attach_interrupt(TIMER2,TIMER_CH2,buzzer_handler); // start timer2 buzz_count=0; timer_generate_update(TIMER2); // refresh timer count, prescale, overflow timer_resume(TIMER2); }
static void timer_setup(void) { /* Set up the timer TIM2 for injected sampling */ uint32_t timer; timer = TIM2; rcc_periph_clock_enable(RCC_TIM2); /* Time Base configuration */ timer_reset(timer); timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(timer, 0xFF); timer_set_prescaler(timer, 0x8); timer_set_clock_division(timer, 0x0); /* Generate TRGO on every update. */ timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); timer_enable_counter(timer); }
void delay_ms(sGrpDev* pGrpDev, uint32_t nCount) { volatile uint16_t TIMCounter;// = nCount; uint16_t cnt2; /* Counter enable. */ /* Reset prescaler value. */ timer_set_prescaler(pGrpDev->pTimer, 7200); timer_direction_down(pGrpDev->pTimer); timer_enable_counter(pGrpDev->pTimer); for (cnt2 = 0; cnt2 < 750; cnt2++) { TIMCounter = nCount; timer_set_counter(pGrpDev->pTimer, TIMCounter); /* Start timer. */ TIM_CR1(pGrpDev->pTimer) |= TIM_CR1_CEN; while (TIMCounter > 1) { TIMCounter = timer_get_counter(pGrpDev->pTimer); } } timer_disable_counter(pGrpDev->pTimer); }
void timer_setup(void) { rcc_periph_clock_enable(RCC_TIM2); nvic_enable_irq(NVIC_TIM2_IRQ); nvic_set_priority(NVIC_TIM2_IRQ, 1); timer_reset(TIM2); /* Timer global mode: - No Divider, Alignment edge, Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM2); /* Set timer prescaler. 72MHz/1440 => 50000 counts per second. */ timer_set_prescaler(TIM2, 1440); /* End timer value. When this is reached an interrupt is generated. */ timer_set_period(TIM2, BLINK_INTERVAL); /* Update interrupt enable. */ timer_enable_irq(TIM2, TIM_DIER_UIE); /* Start timer. */ timer_enable_counter(TIM2); }
void hbridge_init() { // M- bridge // A9 - pin 21 - PWM2A - HIN // B0 - pin 15 - PWM2B - \LIN // M+ bridge // A8 - pin 20 - PWM1A - HIN // A7 - pin 14 - PWM1B - \LIN rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_TIM1EN); AFIO_MAPR |= AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP; gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7 | GPIO8 | GPIO9); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO0); timer_reset(TIM1); timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); timer_set_period(TIM1, half_period_ticks); timer_set_prescaler(TIM1, 9); // / 10 timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_polarity_low(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_set_oc_value(TIM1, TIM_OC1, half_period_ticks); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM2); timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_polarity_low(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_set_oc_value(TIM1, TIM_OC2, half_period_ticks); timer_enable_break_main_output(TIM1); timer_enable_counter(TIM1); }
void gps_init() { int ok; calculate_crc_and_ack(set_navmode, sizeof(set_navmode)); cm3_assert(set_navmode[sizeof(set_navmode) - 2] == 94); cm3_assert(set_navmode[sizeof(set_navmode) - 1] == 235); cm3_assert(expect_ack[8] == 49); cm3_assert(expect_ack[9] == 89); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO2); gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO3); usart_set_baudrate(USART2, 9600); usart_set_databits(USART2, 8); usart_set_stopbits(USART2, USART_STOPBITS_1); usart_set_mode(USART2, USART_MODE_TX); usart_set_parity(USART2, USART_PARITY_NONE); usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE); usart_enable(USART2); timer_reset(TIM5); timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 2Hz */ timer_set_prescaler(TIM5, 640); timer_set_period(TIM5, 28125); ok = silence_nmea(); if (!ok) goto bail; ok = command(set_port, sizeof(set_port)); if (!ok) goto bail; bail: asm("nop"); }
static void platform_init_freqsensor(unsigned char pin) { uint32_t tim; switch(pin) { case 1: /* TIM1 CH1 */ tim = TIM1; gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8); gpio_set_af(GPIOA, GPIO_AF1, GPIO8); break; }; timer_reset(tim); timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(tim, 0xFFFFFFFF); timer_disable_preload(tim); timer_continuous_mode(tim); /* Setup output compare registers */ timer_disable_oc_output(tim, TIM_OC1); timer_disable_oc_output(tim, TIM_OC2); timer_disable_oc_output(tim, TIM_OC3); timer_disable_oc_output(tim, TIM_OC4); /* Set up compare */ timer_ic_set_input(tim, TIM_IC1, TIM_IC_IN_TI1); timer_ic_set_filter(tim, TIM_IC1, TIM_IC_CK_INT_N_8); timer_ic_set_polarity(tim, TIM_IC1, TIM_IC_RISING); timer_set_prescaler(tim, 2*SENSOR_FREQ_DIVIDER); /* Prescale set to map up to 20kHz */ timer_slave_set_mode(tim, TIM_SMCR_SMS_RM); timer_slave_set_trigger(tim, TIM_SMCR_TS_IT1FP1); timer_ic_enable(tim, TIM_IC1); timer_enable_counter(tim); timer_enable_irq(tim, TIM_DIER_CC1IE); switch(pin) { case 1: nvic_enable_irq(NVIC_TIM1_CC_IRQ); nvic_set_priority(NVIC_TIM1_CC_IRQ, 64); break; } }
void freq_capture_setup(void) { /* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */ rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11); gpio_set_af(GPIOE, GPIO_AF1, GPIO11); /* Timer1: Input compare */ /* Enable timer clock. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); /* Reset timer. */ timer_reset(TIM1); /* Configure timer1. */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, // Internal clock TIM_CR1_CMS_EDGE, // Edge synchronization TIM_CR1_DIR_UP); // Count upward timer_set_prescaler(TIM1, TIMER1_PRESCALER); timer_set_period(TIM1, TIMER1_PERIOD); //Sets TIM1_ARR timer_continuous_mode(TIM1); /* Configure PE13: Toggle pin on falling edge via interrupt */ //rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO13); /* Configure input capture. */ timer_ic_disable(TIM1, TIM_IC2); timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF); timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2); // See RM, p. 561: digital filter //timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_DTF_DIV_32_N_8); timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF); timer_ic_enable(TIM1, TIM_IC2); /* Enable counter. */ timer_enable_counter(TIM1); timer_clear_flag (TIM1, TIM_SR_CC2IF); /* Enable IRQs */ nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_CC_IRQ); timer_enable_irq(TIM1, TIM_DIER_CC2IE); }
void BACKLIGHT_Init() { rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN); //Turn off backlight gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); //Configure Backlight PWM rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(TIM3, 0x2CF); timer_set_prescaler(TIM3, 0); timer_generate_event(TIM3, TIM_EGR_UG); //timer_set_repetition_counter(TIM3, 0); timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); timer_enable_oc_preload(TIM3, TIM_OC4); timer_set_oc_polarity_high(TIM3, TIM_OC4); timer_enable_oc_output(TIM3, TIM_OC4); timer_enable_preload(TIM3); }
int timer_init(const uint8_t timer, const timer_operation_mode mode, const timer_prescaler prescaler, const uint16_t preset) { // Initialize result int res = TIMER_ERROR_SUCCESS; // Disable timer first res = timer_disable(timer); if (res == TIMER_ERROR_SUCCESS) { // Set timer operation mode res = timer_set_mode(timer, mode); if (res == TIMER_ERROR_SUCCESS) { // Set preset value res = timer_set(timer, preset); if (res == TIMER_ERROR_SUCCESS) { // Set prescaler value and enable timer res = timer_set_prescaler(timer, prescaler); } } } return res; }
static void timer_setup(void) { /* Set up the timer TIM2 for injected sampling */ uint32_t timer; volatile uint32_t *rcc_apbenr; uint32_t rcc_apb; timer = TIM2; rcc_apbenr = &RCC_APB1ENR; rcc_apb = RCC_APB1ENR_TIM2EN; rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb); /* Time Base configuration */ timer_reset(timer); timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(timer, 0xFF); timer_set_prescaler(timer, 0x8); timer_set_clock_division(timer, 0x0); /* Generate TRGO on every update. */ timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); timer_enable_counter(timer); }
// Adafruit Modification to change PWM Period/Frequency void pwmPeriod(uint8 pin, uint32 us) { if (pin >= BOARD_NR_GPIO_PINS) return; timer_dev *dev = PIN_MAP[pin].timer_device; if (dev == NULL || dev->type == TIMER_BASIC) return; // Get timer's max speed in hz uint32 max_speed = rcc_dev_timer_clk_speed(dev->clk_id); // period in cpu cycles uint32 cycle = us * (max_speed / 1000000UL); uint16 prescaler = (uint16) (cycle / TIMER_MAX_RELOAD); uint16 reload = (uint16) round(cycle / (prescaler+1)); // Re-map compare to preserve duty cycle uint16 compare = timer_get_compare(dev, PIN_MAP[pin].timer_channel); compare = map(compare, 0, timer_get_reload(dev), 0, reload); timer_set_prescaler(dev, prescaler); timer_set_reload(dev, reload); timer_set_compare(dev, PIN_MAP[pin].timer_channel, compare); }
static void timer_setup(void) { /* Enable TIM3 clock. */ rcc_periph_clock_enable(RCC_TIM3); timer_reset(TIM3); /* Timer global mode: - No divider, Alignment edge, Direction up */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM3); timer_set_period(TIM3, PERIOD); timer_disable_preload(TIM3); /* prescaler F_SYS/48 = TIM3 clock is 1 MHz */ timer_set_prescaler(TIM3,48); //timer_disable_oc_output(TIM3, TIM_OC2 | TIM_OC3 | TIM_OC4); timer_enable_oc_output(TIM3, TIM_OC1); timer_disable_oc_output(TIM3,TIM_OC2); timer_enable_oc_output(TIM3, TIM_OC3); //timer_enable_oc_output(TIM3, TIM_OC4); // motor ch1 timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1); // motor ch2 timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); /* disable preload */ timer_disable_oc_preload(TIM3, TIM_OC1); timer_disable_oc_preload(TIM3, TIM_OC2); timer_disable_oc_preload(TIM3, TIM_OC3); timer_disable_oc_preload(TIM3, TIM_OC4); /* polarity */ timer_set_oc_polarity_high(TIM3,TIM_OC1); timer_set_oc_polarity_high(TIM3,TIM_OC2); timer_set_oc_polarity_high(TIM3,TIM_OC3); timer_set_oc_polarity_high(TIM3,TIM_OC4); //timer_enable_oc_clear(TIM3, TIM_OC1); //timer_set_oc_slow_mode(TIM3, TIM_OC1); timer_set_oc_value(TIM3, TIM_OC1, PULSE); timer_set_oc_value(TIM3, TIM_OC2, PULSE*3); timer_set_oc_value(TIM3, TIM_OC3, PULSE*2); timer_set_oc_value(TIM3, TIM_OC4, PULSE*4); //timer_generate_event(TIM3,TIM_EGR_CC1G); //timer_enable_update_event(TIM3); nvic_enable_irq(NVIC_TIM3_IRQ); timer_enable_irq(TIM3,TIM_DIER_CC1IE); timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_CC3IE); timer_enable_irq(TIM3,TIM_DIER_CC4IE); //timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_UIE); /* Set the timer trigger output (for the DAC) to the channel 1 output compare */ //timer_set_master_mode(TIM3, TIM_CR2_MMS_COMPARE_OC1REF); timer_enable_counter(TIM3); }
static void set_prescale(timer_dev *dev) { timer_set_prescaler(dev, init_all_timers_prescale); }
void PID_tim_init(void) { /* Enable TIM1 clock. and Port E clock (for outputs) */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //Set TIM1 channel (and complementary) output to alternate function push-pull'. //f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3 //f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13); gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13); gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12); gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12); /* Enable TIM1 commutation interrupt. */ //nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4 /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now. TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE //TIM_CR1_CMS_CENTER_1 //TIM_CR1_CMS_CENTER_2 //TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal) TIM_CR1_DIR_UP); timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed) timer_set_repetition_counter(TIM1, 0); //disabled timer_enable_preload(TIM1); timer_continuous_mode(TIM1); /* Period (32kHz). */ timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter) /* Configure break and deadtime. */ //timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR); timer_set_enabled_off_state_in_idle_mode(TIM1); timer_set_enabled_off_state_in_run_mode(TIM1); timer_disable_break(TIM1); timer_set_break_polarity_high(TIM1); timer_disable_break_automatic_output(TIM1); timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC1N); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC2N); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC3N); /* -- OC1 and OC1N configuration -- */ /* Configure global mode of line 1. */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); /* Configure OC1. */ timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output /* Configure OC1N. */ timer_set_oc_polarity_high(TIM1, TIM_OC1N); timer_set_oc_idle_state_unset(TIM1, TIM_OC1N); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC2 and OC2N configuration -- */ /* Configure global mode of line 2. */ timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); /* Configure OC2. */ timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_idle_state_unset(TIM1, TIM_OC2); /* Configure OC2N. */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); timer_set_oc_idle_state_unset(TIM1, TIM_OC2N); /* Set the capture compare value for OC2. */ timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC3 and OC3N configuration -- */ /* Configure global mode of line 3. */ timer_enable_oc_preload(TIM1, TIM_OC3); timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); /* Configure OC3. */ timer_set_oc_polarity_high(TIM1, TIM_OC3); timer_set_oc_idle_state_unset(TIM1, TIM_OC3); /* Configure OC3N. */ timer_set_oc_polarity_high(TIM1, TIM_OC3N); timer_set_oc_idle_state_unset(TIM1, TIM_OC3N); /* Set the capture compare value for OC3. */ timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100); /* Reenable outputs. */ timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC3); timer_enable_oc_output(TIM1, TIM_OC3N); /* ---- */ /* ARR reload enable. */ timer_enable_preload(TIM1); /* * Enable preload of complementary channel configurations and * update on COM event. */ //timer_enable_preload_complementry_enable_bits(TIM1); timer_disable_preload_complementry_enable_bits(TIM1); /* Enable outputs in the break subsystem. */ timer_enable_break_main_output(TIM1); /* Generate update event to reload all registers before starting*/ timer_generate_event(TIM1, TIM_EGR_UG); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_COMIE); /*********/ /*Capture compare interrupt*/ //enable capture compare interrupt timer_enable_update_event(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); }
static void tim_setup(void) { /* Enable TIM1 clock. */ rcc_periph_clock_enable(RCC_TIM1); /* Configure TIM1_CH1 and TIM1_CH2 as inputs */ gpio_set_mode(GPIO_BANK_TIM1_CH1, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH1); gpio_set_mode(GPIO_BANK_TIM1_CH2, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_TIM1_CH2); /* Enable TIM1 interrupt. */ nvic_enable_irq(NVIC_TIM1_CC_IRQ); /* Reset TIM1 peripheral. */ /* timer_reset(TIM1); */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* set prescaler value -> 1us */ timer_set_prescaler(TIM1, 72 - 1); timer_set_period(TIM1, 0xFFFF); timer_set_repetition_counter(TIM1, 0); /* Enable preload */ /* timer_disable_preload(TIM1); */ /* Continous mode */ timer_continuous_mode(TIM1); /* configure Channel 1 */ timer_ic_set_input(TIM1, TIM_IC1, TIM_IC_IN_TI1); timer_ic_set_filter(TIM1, TIM_IC1, TIM_IC_OFF); timer_ic_set_polarity(TIM1, TIM_IC1, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC1, TIM_IC_PSC_OFF); timer_ic_enable(TIM1, TIM_IC1); timer_clear_flag(TIM1, TIM_SR_CC1IF); timer_enable_irq(TIM1, TIM_DIER_CC1IE); /* configure Channel 2 */ timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2); timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF); timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF); timer_ic_enable(TIM1, TIM_IC2); timer_clear_flag(TIM1, TIM_SR_CC2IF); timer_enable_irq(TIM1, TIM_DIER_CC2IE); timer_enable_counter(TIM1); #if 0 /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC4); /* -- OC1 configuration -- */ /* Configure global mode of line 1. */ timer_disable_oc_clear(TIM1, TIM_OC1); timer_disable_oc_preload(TIM1, TIM_OC1); timer_set_oc_slow_mode(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, 1000); /* ---- */ /* ARR reload enable. */ timer_disable_preload(TIM1); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ timer_enable_irq(TIM1, TIM_DIER_CC1IE); #endif }
void speaker_setPrescaleFactor(uint32 factor) { timer_set_prescaler(SPEAKER_TIMER, (uint16)(factor - 1)); }
int timer_disable(const uint8_t timer) { // Disabling the prescaler clock is disabling the whole timer return timer_set_prescaler(timer, TPS_DISABLED); }
void HardwareTimer::setPrescaleFactor(uint32 factor) { timer_set_prescaler(this->dev, (uint16)(factor - 1)); }
static void tim_setup(void) { /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); /* Enable TIM2 interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); /* Reset TIM2 peripheral. */ timer_reset(TIM2); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Reset prescaler value. * Running the clock at 5kHz. */ /* * On STM32F4 the timers are not running directly from pure APB1 or * APB2 clock busses. The APB1 and APB2 clocks used for timers might * be the double of the APB1 and APB2 clocks. This depends on the * setting in DCKCFGR register. By default the behaviour is the * following: If the Prescaler APBx is greater than 1 the derived timer * APBx clocks will be double of the original APBx frequencies. Only if * the APBx prescaler is set to 1 the derived timer APBx will equal the * original APBx frequencies. * * In our case here the APB1 is devided by 4 system frequency and APB2 * divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will * be 2 x APB2. So when we try to calculate the prescaler value we have * to use rcc_apb1_freqency * 2!!! * * For additional information see reference manual for the stm32f4 * familiy of chips. Page 204 and 213 */ timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000)); /* Enable preload. */ timer_disable_preload(TIM2); /* Continous mode. */ timer_continuous_mode(TIM2); /* Period (36kHz). */ timer_set_period(TIM2, 65535); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); /* -- OC1 configuration -- */ /* Configure global mode of line 1. */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM2, TIM_OC1, 1000); /* ---- */ /* ARR reload enable. */ timer_disable_preload(TIM2); /* Counter enable. */ timer_enable_counter(TIM2); /* Enable commutation interrupt. */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); }
/** * Commutation timer hardware initialization. */ void comm_tim_init(void) { comm_tim_data.freq = 65535; (void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq)); /* TIM2 clock enable */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); /* Enable the TIM2 gloabal interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); /* Reset TIM2 peripheral. */ timer_reset(TIM2); /* TIM2 time base configuration */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Set prescaler value */ timer_set_prescaler(TIM2, 4); /* Disable preload. */ timer_disable_preload(TIM2); /* Set continous mode. */ timer_continuous_mode(TIM2); /* Set period to maximum */ timer_set_period(TIM2, 65535); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); /* TIM2 Output Compare Timing Mode configuration: Channel1 */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); //timer_set_oc_polarity_high(TIM2, TIM_OC1); /* Set initial capture compare value for OC1 */ timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq); /* ARR reload enable */ timer_disable_preload(TIM2); /* Counter enable */ timer_enable_counter(TIM2); /* TIM2 Capture Compare 1 IT enable */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); /* TIM2 Update IT enable */ timer_enable_irq(TIM2, TIM_DIER_UIE); comm_tim_reset(); }
void motor_TIMER_config(void) { timer_period = rcc_ppre1_frequency / 5000; timer_reset(TIM3); /* set timer mode no divider ; alignment on edge ; direction up */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM3); /* Period (5kHz). TIM3 clk source is APB1*/ timer_set_period(TIM3, timer_period); /* Reset prescaler value. */ timer_set_prescaler(TIM3, 0); motor_front_left = 0; motor_rear_left = 0; motor_front_rigth = 0; motor_rear_rigth = 0; /************ channels configuration ************/ timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT); timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT); timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT); timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT); //configure OCx line timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_LEFT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_LEFT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_RIGHT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_RIGHT, TIM_OCM_PWM1); //configure OCx output timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_RIGHT); /* Set the capture compare value */ timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_LEFT, motor_front_left); timer_set_oc_value(TIM3, MOTOR_PWM_REAR_LEFT, motor_rear_left); timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_RIGHT, motor_front_rigth); timer_set_oc_value(TIM3, MOTOR_PWM_REAR_RIGHT, motor_rear_rigth); timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT); timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT); timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT); timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_enable_counter(TIM3); }
void actuators_pwm_arch_init(void) { /*----------------------------------- * Configure timer peripheral clocks *-----------------------------------*/ /* TIM3, TIM4 and TIM5 clock enable */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); #if REMAP_SERVOS_5AND6 rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM5EN); #else rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN); #endif #if USE_SERVOS_7AND8 rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN); #endif /*---------------- * Configure GPIO *----------------*/ /* GPIO A,B and C clock enable */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN); /* TIM3 GPIO for PWM1..4 */ AFIO_MAPR |= AFIO_MAPR_TIM3_REMAP_FULL_REMAP; gpio_set_mode(GPIO_BANK_TIM3_FR, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM3_FR_CH1 | GPIO_TIM3_FR_CH2 | GPIO_TIM3_FR_CH3 | GPIO_TIM3_FR_CH4); /* TIM4 GPIO for PWM7..8 */ #if USE_SERVOS_7AND8 gpio_set_mode(GPIO_BANK_TIM4, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM4_CH1 | GPIO_TIM4_CH2); #endif /* TIM4/5 GPIO for PWM6..7 */ #if REMAP_SERVOS_5AND6 gpio_set_mode(GPIO_BANK_TIM5, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM5_CH1 | GPIO_TIM5_CH2); #else gpio_set_mode(GPIO_BANK_TIM4, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM4_CH3 | GPIO_TIM4_CH4); #endif /*--------------- * Timer 3 setup *---------------*/ timer_reset(TIM3); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM3, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM3); timer_continuous_mode(TIM3); timer_set_period(TIM3, (ONE_MHZ_CLK / SERVO_HZ) - 1); /* Disable outputs. */ timer_disable_oc_output(TIM3, TIM_OC1); timer_disable_oc_output(TIM3, TIM_OC2); timer_disable_oc_output(TIM3, TIM_OC3); timer_disable_oc_output(TIM3, TIM_OC4); /* -- Channel configuration -- */ actuators_pwm_arch_channel_init(TIM3, TIM_OC1); actuators_pwm_arch_channel_init(TIM3, TIM_OC2); actuators_pwm_arch_channel_init(TIM3, TIM_OC3); actuators_pwm_arch_channel_init(TIM3, TIM_OC4); /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(TIM3, TIM_OC1, 1000); //timer_set_oc_value(TIM3, TIM_OC2, 1000); //timer_set_oc_value(TIM3, TIM_OC3, 1000); //timer_set_oc_value(TIM3, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM3); /* Counter enable. */ timer_enable_counter(TIM3); #if (!REMAP_SERVOS_5AND6 || USE_SERVOS_7AND8) #if !REMAP_SERVOS_5AND6 #pragma message "Not remapping servos 5 and 6 using PB8 and PB9 -> TIM4" #endif #if USE_SERVOS_7AND8 #pragma message "Enabeling sevros 7 and 8 on PB6, PB7 -> TIM4" #endif /*--------------- * Timer 4 setup *---------------*/ timer_reset(TIM4); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM4, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM4); timer_continuous_mode(TIM4); #ifdef SERVO_HZ_SECONDARY timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1); #else timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ) - 1); #endif /* Disable outputs. */ #if USE_SERVOS_7AND8 timer_disable_oc_output(TIM4, TIM_OC1); timer_disable_oc_output(TIM4, TIM_OC2); #endif #if !REMAP_SERVOS_5AND6 timer_disable_oc_output(TIM4, TIM_OC3); timer_disable_oc_output(TIM4, TIM_OC4); #endif /* -- Channel configuration -- */ #if USE_SERVOS_7AND8 actuators_pwm_arch_channel_init(TIM4, TIM_OC1); actuators_pwm_arch_channel_init(TIM4, TIM_OC2); #endif #if !REMAP_SERVOS_5AND6 actuators_pwm_arch_channel_init(TIM4, TIM_OC3); actuators_pwm_arch_channel_init(TIM4, TIM_OC4); #endif /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ #if USE_SERVOS_7AND8 //timer_set_oc_value(TIM4, TIM_OC1, 1000); //timer_set_oc_value(TIM4, TIM_OC2, 1000); #endif #if ! REMAP_SERVOS_5AND6 //timer_set_oc_value(TIM4, TIM_OC3, 1000); //timer_set_oc_value(TIM4, TIM_OC4, 1000); #endif /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM4); /* Counter enable. */ timer_enable_counter(TIM4); #endif #if REMAP_SERVOS_5AND6 #pragma message "Remapping servo outputs 5 and 6 to PA0,PA1 -> TIM5" /*--------------- * Timer 5 setup *---------------*/ timer_reset(TIM5); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM5, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM5); timer_continuous_mode(TIM5); #ifdef SERVO_HZ_SECONDARY timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1); #else timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ) - 1); #endif /* Disable outputs. */ timer_disable_oc_output(TIM5, TIM_OC1); timer_disable_oc_output(TIM5, TIM_OC2); /* -- Channel configuration -- */ actuators_pwm_arch_channel_init(TIM5, TIM_OC1); actuators_pwm_arch_channel_init(TIM5, TIM_OC2); /* * Set the capture compare value for OC1. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(TIM5, TIM_OC1, 1000); //timer_set_oc_value(TIM5, TIM_OC2, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM5); /* Counter enable. */ timer_enable_counter(TIM5); #endif }
/** Set Timer configuration */ static inline void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) { timer_reset(timer); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ if ((timer == TIM9) || (timer == TIM12)) //There are no EDGE and DIR settings in TIM9 and TIM12 timer_set_mode(timer, TIM_CR1_CKD_CK_INT, 0, 0); else timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // TIM1, 8 and 9 use APB2 clock, all others APB1 if (timer != TIM1 && timer != TIM8 && timer != TIM9) { timer_set_prescaler(timer, (TIMER_APB1_CLK / ONE_MHZ_CLK) - 1); // 1uS } else { // TIM9, 1 and 8 use APB2 clock timer_set_prescaler(timer, (TIMER_APB2_CLK / ONE_MHZ_CLK) - 1); } timer_disable_preload(timer); timer_continuous_mode(timer); timer_set_period(timer, (ONE_MHZ_CLK / period) - 1); /* Disable outputs and configure channel if needed. */ if (bit_is_set(channels_mask, 0)) { actuators_pwm_arch_channel_init(timer, TIM_OC1); } if (bit_is_set(channels_mask, 1)) { actuators_pwm_arch_channel_init(timer, TIM_OC2); } if (bit_is_set(channels_mask, 2)) { actuators_pwm_arch_channel_init(timer, TIM_OC3); } if (bit_is_set(channels_mask, 3)) { actuators_pwm_arch_channel_init(timer, TIM_OC4); } /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(timer, TIM_OC1, 1000); //timer_set_oc_value(timer, TIM_OC2, 1000); //timer_set_oc_value(timer, TIM_OC3, 1000); //timer_set_oc_value(timer, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(timer); /* Counter enable. */ timer_enable_counter(timer); }
/** Set Timer configuration * @param[in] timer Timer register address base * @param[in] period period in us * @param[in] channels_mask output compare channels to enable */ void set_servo_timer(uint32_t timer, uint32_t period, uint8_t channels_mask) { // WARNING, this reset is only implemented for TIM1-8 in libopencm3!! timer_reset(timer); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ if ((timer == TIM9) || (timer == TIM12)) //There are no EDGE and DIR settings in TIM9 and TIM12 timer_set_mode(timer, TIM_CR1_CKD_CK_INT, 0, 0); else timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // By default the PWM_BASE_FREQ is set to 1MHz thus the timer tick period is 1uS uint32_t timer_clk = timer_get_frequency(timer); timer_set_prescaler(timer, (timer_clk / PWM_BASE_FREQ) -1); timer_disable_preload(timer); timer_continuous_mode(timer); timer_set_period(timer, (PWM_BASE_FREQ / period) - 1); /* Disable outputs and configure channel if needed. */ if (bit_is_set(channels_mask, 0)) { actuators_pwm_arch_channel_init(timer, TIM_OC1); } if (bit_is_set(channels_mask, 1)) { actuators_pwm_arch_channel_init(timer, TIM_OC2); } if (bit_is_set(channels_mask, 2)) { actuators_pwm_arch_channel_init(timer, TIM_OC3); } if (bit_is_set(channels_mask, 3)) { actuators_pwm_arch_channel_init(timer, TIM_OC4); } /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(timer, TIM_OC1, 1000); //timer_set_oc_value(timer, TIM_OC2, 1000); //timer_set_oc_value(timer, TIM_OC3, 1000); //timer_set_oc_value(timer, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(timer); /* Counter enable. */ timer_enable_counter(timer); }
void accel_highg_init() { uint8_t channel_array[16]; gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0 | GPIO1 | GPIO2); adc_set_dual_mode(ADC_CR1_DUALMOD_RSM); /* ADC1 + ADC2 dual mode */ adc_set_dual_mode(ADC_CR1_DUALMOD_ISM); adc_enable_external_trigger_injected(ADC1, ADC_CR2_JEXTSEL_TIM1_TRGO); adc_enable_external_trigger_injected(ADC3, ADC_CR2_JEXTSEL_TIM1_TRGO); adc_enable_dma(ADC1); adc_enable_dma(ADC3); adc_power_on(ADC1); adc_power_on(ADC2); adc_power_on(ADC3); adc_stab_sleep(); adc_reset_calibration(ADC1); adc_reset_calibration(ADC2); adc_reset_calibration(ADC3); adc_calibration(ADC1); adc_calibration(ADC2); adc_calibration(ADC3); memset(channel_array, 0, sizeof(channel_array)); channel_array[0] = 10; adc_set_injected_sequence(ADC1, 1, channel_array); channel_array[0] = 11; adc_set_injected_sequence(ADC2, 1, channel_array); channel_array[0] = 12; adc_set_injected_sequence(ADC3, 1, channel_array); timer_reset(TIM1); timer_enable_irq(TIM1, TIM_DIER_UIE); timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* 500Hz */ timer_set_prescaler(TIM1, 64); timer_set_period(TIM1, 2250); /* Generate TRGO */ timer_set_master_mode(TIM1, TIM_CR2_MMS_UPDATE); dma_set_peripheral_address(DMA1, DMA_CHANNEL5, (uint32_t) &ADC1_DR); dma_set_read_from_memory(DMA1, DMA_CHANNEL5); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL5); dma_set_peripheral_size(DMA1, DMA_CHANNEL5, DMA_CCR_PSIZE_32BIT); dma_set_memory_size(DMA1, DMA_CHANNEL5, DMA_CCR_MSIZE_32BIT); dma_set_priority(DMA1, DMA_CHANNEL5, DMA_CCR_PL_HIGH); dma_set_peripheral_address(DMA1, DMA_CHANNEL6, (uint32_t) &ADC3_DR); dma_set_read_from_peripheral(DMA1, DMA_CHANNEL6); dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL6); dma_set_peripheral_size(DMA1, DMA_CHANNEL6, DMA_CCR_PSIZE_16BIT); dma_set_memory_size(DMA1, DMA_CHANNEL6, DMA_CCR_MSIZE_16BIT); dma_set_priority(DMA1, DMA_CHANNEL6, DMA_CCR_PL_HIGH); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL5); dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL6); }