void romstage_init(void)
{
void *entry;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
rkclk_set_pll();
console_init();
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
dram_main();
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
udelay(100);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);
#endif
stage_exit(entry);
}
void main(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
console_init();
configure_l2ctlr();
tsadc_init();
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
sdram_init(get_sdram_config());
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
void *entry = vboot2_load_ramstage();
if (entry != NULL)
stage_exit(entry);
#endif
run_ramstage();
}
void stopwatch_stop(struct stopwatch *timer, const struct timestamp *now)
{
if ((STOPWATCH_ACTIVE(timer))) {
timestamp_add(&timer->total, now);
timestamp_sub(&timer->total, &timer->start);
timestamp_init(&timer->start);
} else {
//DEBUG_ONLY(NONFATAL("Stopping inactive stopwatch."));
}
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
struct romstage_handoff *handoff;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time =
(uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 ||
pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
start_romstage_time = timestamp_get();
#endif
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = wake_from_s3;
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
timestamp_add_now(TS_END_ROMSTAGE);
#endif
}
int main(int argc, char *argv[])
{
unsigned long sleep_time;
double read_interval;
start_time = time(0);
memset(&rtiming, 0, sizeof(rtiming));
rtiming.rt_variance.v_min = FLT_MAX;
/*
* Early initialization before reading config
*/
conf_init_pre();
parse_args_pre(argc, argv);
/*
* Reading the configuration file */
configfile_read();
/*
* Late initialization after reading config
*/
if (parse_args_post(argc, argv))
return 1;
conf_init_post();
module_init();
read_interval = cfg_read_interval;
sleep_time = cfg_getint(cfg, "sleep_time");
if (((double) sleep_time / 1000000.0f) > read_interval)
sleep_time = (unsigned long) (read_interval * 1000000.0f);
DBG("Entering mainloop...");
do {
/*
* E := Elapsed time
* NR := Next Read
* LR := Last Read
* RI := Read Interval
* ST := Sleep Time
* C := Correction
*/
timestamp_t e, ri, tmp;
unsigned long st;
float_to_timestamp(&ri, read_interval);
/*
* NR := NOW
*/
update_timestamp(&rtiming.rt_next_read);
for (;;) {
output_pre();
/*
* E := NOW
*/
update_timestamp(&e);
/*
* IF NR <= E THEN
*/
if (timestamp_le(&rtiming.rt_next_read, &e)) {
timestamp_t c;
/*
* C := (NR - E)
*/
timestamp_sub(&c, &rtiming.rt_next_read, &e);
//calc_variance(&c, &ri);
/*
* LR := E
*/
copy_timestamp(&rtiming.rt_last_read, &e);
/*
* NR := E + RI + C
*/
timestamp_add(&rtiming.rt_next_read, &e, &ri);
timestamp_add(&rtiming.rt_next_read,
&rtiming.rt_next_read, &c);
reset_update_flags();
input_read();
free_unused_elements();
output_draw();
output_post();
}
if (do_quit)
exit(0);
/*
* ST := Configured ST
*/
st = sleep_time;
/*
* IF (NR - E) < ST THEN
*/
timestamp_sub(&tmp, &rtiming.rt_next_read, &e);
if (tmp.tv_sec < 0)
continue;
if (tmp.tv_sec == 0 && tmp.tv_usec < st) {
if (tmp.tv_usec < 0)
continue;
/*
* ST := (NR - E)
*/
st = tmp.tv_usec;
}
/*
* SLEEP(ST)
*/
usleep(st);
}
} while (0);
return 0; /* buddha says i'll never be reached */
}
void timestamp_add_now(enum timestamp_id id)
{
timestamp_add(id, timestamp_get());
}
static int hash_body(struct vb2_context *ctx, struct region_device *fw_main)
{
uint64_t load_ts;
uint32_t expected_size;
uint8_t block[TODO_BLOCK_SIZE];
uint8_t hash_digest[VBOOT_MAX_HASH_SIZE];
const size_t hash_digest_sz = sizeof(hash_digest);
size_t block_size = sizeof(block);
size_t offset;
int rv;
/* Clear the full digest so that any hash digests less than the
* max have trailing zeros. */
memset(hash_digest, 0, hash_digest_sz);
/*
* Since loading the firmware and calculating its hash is intertwined,
* we use this little trick to measure them separately and pretend it
* was first loaded and then hashed in one piece with the timestamps.
* (This split won't make sense with memory-mapped media like on x86.)
*/
load_ts = timestamp_get();
timestamp_add(TS_START_HASH_BODY, load_ts);
expected_size = region_device_sz(fw_main);
offset = 0;
/* Start the body hash */
rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size);
if (rv)
return rv;
/*
* Honor vboot's RW slot size. The expected size is pulled out of
* the preamble and obtained through vb2api_init_hash() above. By
* creating sub region the RW slot portion of the boot media is
* limited.
*/
if (rdev_chain(fw_main, fw_main, 0, expected_size)) {
printk(BIOS_ERR, "Unable to restrict CBFS size.\n");
return VB2_ERROR_UNKNOWN;
}
/* Extend over the body */
while (expected_size) {
uint64_t temp_ts;
if (block_size > expected_size)
block_size = expected_size;
temp_ts = timestamp_get();
if (rdev_readat(fw_main, block, offset, block_size) < 0)
return VB2_ERROR_UNKNOWN;
load_ts += timestamp_get() - temp_ts;
rv = vb2api_extend_hash(ctx, block, block_size);
if (rv)
return rv;
expected_size -= block_size;
offset += block_size;
}
timestamp_add(TS_DONE_LOADING, load_ts);
timestamp_add_now(TS_DONE_HASHING);
/* Check the result (with RSA signature verification) */
rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz);
if (rv)
return rv;
timestamp_add_now(TS_END_HASH_BODY);
if (handle_digest_result(hash_digest, hash_digest_sz))
return VB2_ERROR_UNKNOWN;
return VB2_SUCCESS;
}
/*******************************************************************************
* The FSP early_init function returns to this function.
* Memory is setup and the stack is set by the FSP.
*/
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
int cbmem_was_initted;
void *cbmem_hob_ptr;
uint32_t prev_sleep_state;
struct romstage_handoff *handoff;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
tsc_t after_initram_time = rdtsc();
tsc_t base_time;
base_time.hi = 0;
base_time.lo = 0;
#endif
post_code(0x4a);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
usbdebug_init();
#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
/* Get previous sleep state again and clear */
prev_sleep_state = chipset_prev_sleep_state(1);
printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state);
report_platform_info();
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
after_initram_time = rdtsc();
#endif
post_code(0x4b);
late_mainboard_romstage_entry();
post_code(0x4c);
/* if S3 resume skip ram check */
if (prev_sleep_state != 3) {
quick_ram_check();
post_code(0x4d);
}
cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == 3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
timestamp_init(base_time);
timestamp_reinit();
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
printk(BIOS_DEBUG, "cbmemc_reinit\n");
cbmemc_reinit();
#endif
post_code(0x4f);
/* Load the ramstage. */
copy_and_run();
while (1);
}
int main(int argc, char *argv[])
{
unsigned long sleep_time;
double read_interval;
start_time = time(0);
parse_args_pre(argc, argv);
configfile_read();
parse_args_post(argc, argv);
conf_init();
module_init();
read_interval = cfg_read_interval;
sleep_time = cfg_getint(cfg, "sleep_time");
if (((double) sleep_time / 1000000.0f) > read_interval)
sleep_time = (unsigned long) (read_interval * 1000000.0f);
// pipe_start();
if (cfg_getbool(cfg, "daemon")) {
init_syslog();
daemonize();
write_pidfile();
}
drop_privs();
do {
/*
* E := Elapsed time
* NR := Next Read
* LR := Last Read
* RI := Read Interval
* ST := Sleep Time
* C := Correction
*/
timestamp_t e, ri, tmp;
unsigned long st;
float_to_timestamp(&ri, read_interval);
/*
* NR := NOW
*/
update_timestamp(&rtiming.rt_next_read);
for (;;) {
output_pre();
/*
* read the chucka chucka pipe
*/
// pipe_handle();
/*
* E := NOW
*/
update_timestamp(&e);
/*
* IF NR <= E THEN
*/
if (timestamp_le(&rtiming.rt_next_read, &e)) {
timestamp_t c;
/*
* C := (NR - E)
*/
timestamp_sub(&c, &rtiming.rt_next_read, &e);
//calc_variance(&c, &ri);
/*
* LR := E
*/
copy_timestamp(&rtiming.rt_last_read, &e);
/*
* NR := E + RI + C
*/
timestamp_add(&rtiming.rt_next_read, &e, &ri);
timestamp_add(&rtiming.rt_next_read,
&rtiming.rt_next_read, &c);
reset_update_flags();
input_read();
free_unused_elements();
output_draw();
output_post();
}
if (do_quit)
exit(0);
/*
* ST := Configured ST
*/
st = sleep_time;
/*
* IF (NR - E) < ST THEN
*/
timestamp_sub(&tmp, &rtiming.rt_next_read, &e);
if (tmp.tv_sec < 0)
continue;
if (tmp.tv_sec == 0 && tmp.tv_usec < st) {
if (tmp.tv_usec < 0)
continue;
/*
* ST := (NR - E)
*/
st = tmp.tv_usec;
}
/*
* SLEEP(ST)
*/
usleep(st);
}
} while (0);
return 0; /* buddha says i'll never be reached */
}
