/* In this function we need to use device adresses to map them */ void build_tlb_table(uint32_t *table) { memset(table, 0, 4*4096); tlb_map(table, PHYS_OFFSET, PHYS_OFFSET, 64, TTBL_NORMAL_MAPPING); tlb_map(table, PHYS_OFFSET, PAGE_OFFSET, 64, TTBL_NORMAL_MAPPING); /* Hardware specific mapping */ #ifdef __PLAT_TI_OMAP3430__ tlb_map(table, L2CC_BASE_ADDR, L2CC_BASE_ADDR, 1, TTBL_DEVICE_MAPPING); #endif /* End of hardware specific mapping */ }
void booke_init_tlb(vm_paddr_t fdt_immr_pa) { /* Map register space */ tlb_map(APM86XXX_DEEP_SLEEP_VA, OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA), OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M, TLB_SW | TLB_SR | TLB_I | TLB_G); tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA), OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M, TLB_SW | TLB_SR | TLB_I | TLB_G); tlb_map(APM86XXX_PRIMARY_FABRIC_VA, OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA), OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA), TLB_VALID | TLB_SIZE_16M, TLB_SW | TLB_SR | TLB_I | TLB_G); tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA), OCP_ADDR_WORDHI(APM86XXX_AHB_PA), TLB_VALID | TLB_SIZE_16M, TLB_SW | TLB_SR | TLB_I | TLB_G); /* Map MailBox space */ tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA), OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), TLB_VALID | TLB_SIZE_4K, TLB_UX | TLB_UW | TLB_UR | TLB_SX | TLB_SW | TLB_SR | TLB_I | TLB_G); tlb_map(APM86XXX_MBOX_VA + 0x1000, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000, OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), TLB_VALID | TLB_SIZE_4K, TLB_UX | TLB_UW | TLB_UR | TLB_SX | TLB_SW | TLB_SR | TLB_I | TLB_G); tlb_map(APM86XXX_MBOX_VA + 0x2000, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000, OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), TLB_VALID | TLB_SIZE_4K, TLB_UX | TLB_UW | TLB_UR | TLB_SX | TLB_SW | TLB_SR | TLB_I | TLB_G); }