static WRITE_HANDLER(nuova_pia_b_w) {
if (~data & 0x02) // write
tms5220_data_w(0, locals.pia_a);
if (~data & 0x01) // read
locals.pia_a = tms5220_status_r(0);
pia_set_input_ca2(2, 1);
locals.pia_b = data;
}
void a2bus_echoii_device::write_c0nx(address_space &space, UINT8 offset, UINT8 data)
{
switch (offset)
{
case 0:
tms5220_data_w(m_tms, space, offset, data);
break;
}
}
static WRITE8_HANDLER(tms7041_portd_w)
{
exelv_state *state = space->machine().driver_data<exelv_state>();
device_t *tms5220c = space->machine().device( "tms5220c" );
logerror("tms7041_portd_w: data = 0x%02x\n", data);
tms5220_data_w( tms5220c, 0, BITSWAP8(data,0,1,2,3,4,5,6,7) );
state->m_tms7041_portd = data;
}
static WRITE8_HANDLER( speech_strobe_w )
{
jedi_state *state = space->machine->driver_data<jedi_state>();
int new_speech_strobe_state = (~offset >> 8) & 1;
if ((new_speech_strobe_state != state->speech_strobe_state) && new_speech_strobe_state)
{
running_device *tms = space->machine->device("tms");
tms5220_data_w(tms, 0, *state->speech_data);
}
state->speech_strobe_state = new_speech_strobe_state;
}
static WRITE8_DEVICE_HANDLER( r6532_porta_w )
{
if (has_mc3417)
cputag_set_input_line(device->machine, "cvsdcpu", INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
if (has_tms5220)
{
running_device *tms = devtag_get_device(device->machine, "tms");
logerror("(%f)%s:TMS5220 data write = %02X\n", attotime_to_double(timer_get_time(device->machine)), cpuexec_describe_context(device->machine), riot6532_porta_out_get(riot));
tms5220_data_w(tms, 0, data);
}
}
static WRITE8_DEVICE_HANDLER( r6532_porta_w )
{
exidy_sound_state *state = get_safe_token(device);
if (state->m_cvsd != NULL)
space.machine().device("cvsdcpu")->execute().set_input_line(INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
if (state->m_tms != NULL)
{
logerror("(%f)%s:TMS5220 data write = %02X\n", space.machine().time().as_double(), space.machine().describe_context(), riot6532_porta_out_get(state->m_riot));
tms5220_data_w(state->m_tms, space, 0, data);
}
}
static WRITE8_HANDLER( speech_strobe_w )
{
jedi_state *state = (jedi_state *)space->machine->driver_data;
int new_speech_strobe_state = (~offset >> 8) & 1;
if ((new_speech_strobe_state != state->speech_strobe_state) && new_speech_strobe_state)
{
const device_config *tms = devtag_get_device(space->machine, "tms");
tms5220_data_w(tms, 0, *state->speech_data);
}
state->speech_strobe_state = new_speech_strobe_state;
}
/*
TMS5200 speech chip write
*/
static WRITE8_HANDLER ( geneve_speech_w )
{
activecpu_adjust_icount(-32*4); /* this is just an approx. minimum, it can be much more */
#if 1
/* the stupid design of the tms5220 core means that ready is cleared when
there are 15 bytes in FIFO. It should be 16. Of course, if it were the
case, we would need to store the value on the bus, which would be more
complex. */
if (! tms5220_ready_r())
{
double time_to_ready = tms5220_time_to_ready();
int cycles_to_ready = ceil(TIME_TO_CYCLES(0, time_to_ready));
logerror("time to ready: %f -> %d\n", time_to_ready, (int) cycles_to_ready);
activecpu_adjust_icount(-cycles_to_ready);
timer_set(TIME_NOW, 0, /*speech_kludge_callback*/NULL);
}
#endif
tms5220_data_w(offset, data);
}
void atarisys2_tms5220_strobe_w (int offset, int data)
{
if (!(offset & 1) && tms5220_data_strobe)
tms5220_data_w (0, tms5220_data);
tms5220_data_strobe = offset & 1;
}
void starwars_m6532_w(int offset, int data)
{
switch (offset)
{
case 0: /* 0x80 - Port A Write */
/* Write to speech chip on PA0 falling edge */
if((port_A&0x01)==1)
{
port_A = (port_A&(~port_A_ddr))|(data&port_A_ddr);
if ((port_A&0x01)==0)
tms5220_data_w(0,port_B);
}
else
port_A = (port_A&(~port_A_ddr))|(data&port_A_ddr);
return;
case 1: /* 0x81 - Port A DDR Write */
port_A_ddr = data;
return;
case 2: /* 0x82 - Port B Write */
/* TMS5220 Speech Data on port B */
/* ignore DDR for now */
port_B = data;
return;
case 3: /* 0x83 - Port B DDR Write */
port_B_ddr = data;
return;
case 7: /* 0x87 - Enable Interrupt on PA7 Transitions */
/* This feature is emulated now. When the Main CPU */
/* writes to mainwrite, it may send an IRQ to the */
/* sound CPU, depending on the state of this flag. */
PA7_irq = data;
return;
case 0x1f: /* 0x9f - Set Timer to decrement every n*1024 clocks, */
/* With IRQ enabled on countdown */
/* Should be decrementing every data*1024 6532 clock cycles */
/* 6532 runs at 1.5 Mhz, so there a 3 cylces in 2 usec */
timer_set (TIME_IN_USEC((1024*2/3)*data), 0, snd_interrupt);
return;
default:
return;
}
return; /* will never execute this */
}
static WRITE_HANDLER(out_snd_3) {
if (!q) tms5220_data_w(0, data);
printf("o");
}
static WRITE8_HANDLER( exidy_shriot_w )
{
/* I/O is done if A2 == 0 */
if ((offset & 0x04) == 0)
{
switch (offset & 0x03)
{
case 0: /* port A */
if (has_mc3417)
cpunum_set_input_line(machine, 2, INPUT_LINE_RESET, (data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
riot_porta_data = (riot_porta_data & ~riot_porta_ddr) | (data & riot_porta_ddr);
break;
case 1: /* port A DDR */
riot_porta_ddr = data;
break;
case 2: /* port B */
if (has_tms5220)
{
if (!(data & 0x01) && (riot_portb_data & 0x01))
{
riot_porta_data = tms5220_status_r(machine, 0);
logerror("(%f)%04X:TMS5220 status read = %02X\n", attotime_to_double(timer_get_time()), activecpu_get_previouspc(), riot_porta_data);
}
if (!(data & 0x02) && (riot_portb_data & 0x02))
{
logerror("(%f)%04X:TMS5220 data write = %02X\n", attotime_to_double(timer_get_time()), activecpu_get_previouspc(), riot_porta_data);
tms5220_data_w(machine, 0, riot_porta_data);
}
}
riot_portb_data = (riot_portb_data & ~riot_portb_ddr) | (data & riot_portb_ddr);
break;
case 3: /* port B DDR */
riot_portb_ddr = data;
break;
}
}
/* PA7 edge detect control if A2 == 1 and A4 == 0 */
else if ((offset & 0x10) == 0)
{
riot_PA7_irq_enable = offset & 0x03;
}
/* timer enable if A2 == 1 and A4 == 1 */
else
{
static const int divisors[4] = { 1, 8, 64, 1024 };
/* make sure the IRQ state is clear */
if (riot_state != RIOT_COUNT)
riot_irq_flag &= ~0x80;
riot_irq_state = 0;
update_irq_state(0);
/* set the enable from the offset */
riot_timer_irq_enable = (offset & 0x08) ? 1 : 0;
/* set a new timer */
riot_clock_divisor = divisors[offset & 0x03];
timer_adjust_oneshot(riot_timer, attotime_mul(ATTOTIME_IN_HZ(SH6532_CLOCK), data * riot_clock_divisor), 0);
riot_state = RIOT_COUNT;
}
}
static WRITE8_HANDLER( speech_strobe_w )
{
tms5220_data_w(0, speech_write_buffer);
}
