int timer_init (void)
{
/* Divide clock by TMU_CLK_DIVIDER */
u16 bit = 0;
switch (TMU_CLK_DIVIDER) {
case 1024:
bit = 4;
break;
case 256:
bit = 3;
break;
case 64:
bit = 2;
break;
case 16:
bit = 1;
break;
case 4:
default:
break;
}
writew(readw(TCR0) | bit, TCR0);
/* Clock frequency calc */
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
int timer_init (void)
{
/* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
u16 bit = 0;
switch (CONFIG_SYS_TMU_CLK_DIV) {
case 1024:
bit = 4;
break;
case 256:
bit = 3;
break;
case 64:
bit = 2;
break;
case 16:
bit = 1;
break;
case 4:
default:
break;
}
writew(readw(TCR0) | bit, TCR0);
/* Calc clock rate */
timer_freq = get_tmu0_clk_rate() >> ((bit + 1) * 2);
tmu_timer_stop(0);
tmu_timer_start(0);
last_tcnt = 0;
overflow_ticks = 0;
return 0;
}
void set_timer (unsigned long t)
{
/* Note: timer must be STOPPED to update it */
tmu_timer_stop(0);
writel((0 - t), TCNT0);
tmu_timer_start(0);
}
int timer_init (void)
{
/* Divide clock by 4 */
*(volatile u16 *)TCR0 = 0;
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
int timer_init(void)
{
/* Divide clock by 4 */
outw(0, TCR0);
tmu_timer_stop(0);
tmu_timer_start(0);
return 0;
}
static int tmu_timer_init(void)
{
unsigned long interval;
unsigned long frequency;
setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
tmu0_clk.parent = clk_get(NULL, "module_clk");
tmu1_clk.parent = clk_get(NULL, "module_clk");
tmu_timer_stop();
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
!defined(CONFIG_CPU_SUBTYPE_SH7721) && \
!defined(CONFIG_CPU_SUBTYPE_SH7760) && \
!defined(CONFIG_CPU_SUBTYPE_SH7785) && \
!defined(CONFIG_CPU_SUBTYPE_SHX3)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif
clk_register(&tmu0_clk);
clk_register(&tmu1_clk);
clk_enable(&tmu0_clk);
clk_enable(&tmu1_clk);
frequency = clk_get_rate(&tmu0_clk);
interval = (frequency + HZ / 2) / HZ;
sh_hpt_frequency = clk_get_rate(&tmu1_clk);
ctrl_outl(~0, TMU1_TCNT);
ctrl_outl(~0, TMU1_TCOR);
tmu0_timer_set_interval(interval, 1);
tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
tmu0_clockevent.shift);
tmu0_clockevent.max_delta_ns =
clockevent_delta2ns(-1, &tmu0_clockevent);
tmu0_clockevent.min_delta_ns =
clockevent_delta2ns(1, &tmu0_clockevent);
tmu0_clockevent.cpumask = cpumask_of_cpu(0);
clockevents_register_device(&tmu0_clockevent);
return 0;
}
void reset_timer (void)
{
tmu_timer_stop(0);
set_timer (0);
tmu_timer_start(0);
}