//---------------------------------------------------------------------------- // User rouitine to processing IRQ ( for LPC24XX) //---------------------------------------------------------------------------- void tn_cpu_irq_handler(void) { register int irq_stat; register int rc; int data; irq_stat = VICIRQStatus; //----- Timebase 0.8 ms int (actually this time is set by sending desired value to FPGA) ----- if((irq_stat & (1<<15)) > 0) { // Drop external signal: status = inpw(STATUS); // (Drops interrupt request when read) // Clear EINT1 source: EXTINT = 0x00000002; //semaphore setting to make interrupt processing: tn_sem_isignal(&SemISR); // code from timer interrupt processing. tn_tick_int_processing(); //----- UART TX Helper ---------------------- if((U0LSR & (1<<5))>0) { rc = tn_queue_ireceive(&queueTxUart,(void **)&data); if(rc == TERR_NO_ERR) U0THR = data; } // code from timer interrupt processing - END. } VICVectAddr = 0; }
void sf_uart0_int_handler() { trace(__FILE__,__LINE__,"enter uart0 int handler"); register int rc; register int data; register int i; unsigned int status; unsigned char * rx_buf; status = rU0IIR; // Reset Int Request Source status &= (0x7 <<1); /* RX */ if(status == RX_INT || status == TO_INT) { trace(__FILE__,__LINE__,"uart int: rx event"); rc = tn_fmem_get_ipolling(&RxUART0MemPool, (void **) &rx_buf); if(rc != TERR_NO_ERR) rx_buf = NULL; rc = 0; i = UART_FIFO_SIZE; while((rU0LSR & 0x01) && (i--)) //-- Rx FIFO not empty { data = rU0RBR; if(rx_buf) rx_buf[rc++] = (unsigned char)data; } if(rc > 0) { //--- Pack length & address data = (rc << 24) | (((unsigned int)rx_buf) & 0x00FFFFFF); data = tn_queue_isend_polling(&queueRxUART0, (void *) data); if(data != TERR_NO_ERR) rc = 0; } if(rc == 0 && rx_buf) tn_fmem_irelease(&RxUART0MemPool, (void *) rx_buf); } /* TX */ if(status == TX_INT) { trace(__FILE__,__LINE__,"uart int: releasing semaphore for uart0 tx fifo empty"); tn_sem_isignal(&semFifoEmptyTxUART0); } trace(__FILE__,__LINE__,"exiting uart int"); }