/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = is_running_in_sdram(); watchdog_init(); try_unlock_memory(); /* * Right now flushing at low MPU speed. * Need to move after clock init */ invalidate_dcache(get_device_type()); #ifdef CONFIG_L2_OFF l2_cache_disable(); #else l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); sdelay(100); prcm_init(); per_clocks_enable(); #ifdef CONFIG_USB_EHCI_OMAP ehci_clocks_enable(); #endif #ifdef CONFIG_SPL_BUILD preloader_console_init(); timer_init(); #endif if (!in_sdram) mem_init(); }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. **********************************************************/ void s_init(void) { int i; int external_boot = 0; int in_sdram = running_in_sdram(); watchdog_init(); external_boot = (get_boot_type() == 0x1F) ? 1 : 0; /* Right now flushing at low MPU speed. Need to move after clock init */ v7_flush_dcache_all(get_device_type(), external_boot); try_unlock_memory(); if (cpu_is_3410()) { /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); } #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif set_muxconf_regs(); delay(100); /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ /* Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ setup_auxcr(get_device_type(), external_boot); prcm_init(); per_clocks_enable(); }
/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = is_running_in_sdram(); watchdog_init(); try_unlock_memory(); /* * Right now flushing at low MPU speed. * Need to move after clock init */ v7_flush_dcache_all(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); delay(100); prcm_init(); per_clocks_enable(); if (!in_sdram) sdrc_init(); }