void plat_rockchip_pmusram_prepare(void) { uint32_t *sram_dst, *sram_src; size_t sram_size = 2; uint32_t code_size, data_size; /* pmu sram code and data prepare */ sram_dst = (uint32_t *)PMUSRAM_BASE; sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - (uint32_t *)sram_src; u32_align_cpy(sram_dst, sram_src, sram_size); /* ddr code */ sram_dst += sram_size; sram_src = ddr_get_resume_code_base(); code_size = ddr_get_resume_code_size(); u32_align_cpy(sram_dst, sram_src, code_size / 4); psram_sleep_cfg->ddr_func = (uint64_t)sram_dst; /* ddr data */ sram_dst += (code_size / 4); data_size = ddr_get_resume_data_size(); psram_sleep_cfg->ddr_data = (uint64_t)sram_dst; assert((uint64_t)(sram_dst + data_size / 4) < PSRAM_SP_BOTTOM); psram_sleep_cfg->sp = PSRAM_SP_TOP; }
void plat_rockchip_pmusram_prepare(void) { uint32_t *sram_dst, *sram_src; size_t sram_size = 2; /* * pmu sram code and data prepare */ sram_dst = (uint32_t *)PMUSRAM_BASE; sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - (uint32_t *)sram_src; u32_align_cpy(sram_dst, sram_src, sram_size); psram_sleep_cfg->sp = PSRAM_DT_BASE; }