uint8_t u8g_dev_ssd1322_nhd31oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) { switch(msg) { case U8G_DEV_MSG_INIT: u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS); u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_1bit_nhd_312_init_seq); break; case U8G_DEV_MSG_STOP: break; case U8G_DEV_MSG_PAGE_NEXT: { uint8_t i; u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem); uint8_t *p = pb->buf; u8g_uint_t cnt; cnt = pb->width; cnt >>= 3; for( i = 0; i < pb->p.page_height; i++ ) { u8g_dev_ssd1322_1bit_prepare_row(u8g, dev, i); /* this will also enable chip select */ #if !defined(U8G_16BIT) u8g_WriteByte(u8g, dev, 0x0ff); u8g_WriteByte(u8g, dev, 0x0ff); #endif u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p); #if !defined(U8G_16BIT) u8g_WriteByte(u8g, dev, 0x0ff); u8g_WriteByte(u8g, dev, 0x0ff); #endif u8g_MicroDelay(); // for DUE? u8g_SetChipSelect(u8g, dev, 0); p+=cnt; } } break; case U8G_DEV_MSG_CONTRAST: u8g_SetChipSelect(u8g, dev, 1); u8g_SetAddress(u8g, dev, 0); /* instruction mode */ u8g_WriteByte(u8g, dev, 0x0c1); /* 21 May 2013, fixed contrast command */ u8g_SetAddress(u8g, dev, 1); /* data mode */ u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1); u8g_SetChipSelect(u8g, dev, 0); break; case U8G_DEV_MSG_SLEEP_ON: u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on); return 1; case U8G_DEV_MSG_SLEEP_OFF: u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off); return 1; } return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg); }
uint8_t u8g_dev_t6963_240x128_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) { switch(msg) { case U8G_DEV_MSG_INIT: u8g_InitCom(u8g, dev); u8g_WriteEscSeqP(u8g, dev, u8g_dev_t6963_240x128_init_seq); break; case U8G_DEV_MSG_STOP: break; case U8G_DEV_MSG_PAGE_NEXT: { uint8_t y, i; uint16_t disp_ram_adr; uint8_t *ptr; u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem); u8g_SetAddress(u8g, dev, 0); /* data mode */ u8g_SetChipSelect(u8g, dev, 1); y = pb->p.page_y0; ptr = pb->buf; disp_ram_adr = WIDTH/8; disp_ram_adr *= y; for( i = 0; i < PAGE_HEIGHT; i ++ ) { u8g_SetAddress(u8g, dev, 0); /* data mode */ u8g_WriteByte(u8g, dev, disp_ram_adr&255 ); /* address low byte */ u8g_WriteByte(u8g, dev, disp_ram_adr>>8 ); /* address hight byte */ u8g_SetAddress(u8g, dev, 1); /* cmd mode */ u8g_WriteByte(u8g, dev, 0x024 ); /* set adr ptr */ u8g_WriteSequence(u8g, dev, WIDTH/8, ptr); ptr += WIDTH/8; disp_ram_adr += WIDTH/8; } u8g_SetAddress(u8g, dev, 0); /* data mode */ u8g_SetChipSelect(u8g, dev, 0); } break; } return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg); }
static uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) { switch(msg) { case U8G_DEV_MSG_INIT: u8g_InitCom(u8g, dev); u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_nhd_27_12864_init_seq); break; case U8G_DEV_MSG_STOP: break; case U8G_DEV_MSG_PAGE_NEXT: { uint8_t i; u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem); uint8_t *p = pb->buf; u8g_uint_t cnt; cnt = pb->width; cnt >>= 3; for( i = 0; i < pb->p.page_height; i++ ) { u8g_dev_ssd1325_prepare_row(u8g, dev, i); /* this will also enable chip select */ u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p); u8g_SetChipSelect(u8g, dev, 0); p+=cnt; } } break; case U8G_DEV_MSG_CONTRAST: u8g_SetChipSelect(u8g, dev, 1); u8g_SetAddress(u8g, dev, 0); /* instruction mode */ u8g_WriteByte(u8g, dev, 0x081); u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1); u8g_SetChipSelect(u8g, dev, 0); break; case U8G_DEV_MSG_SLEEP_ON: u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on); return 1; case U8G_DEV_MSG_SLEEP_OFF: u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off); return 1; } return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg); }
uint8_t u8g_dev_rrd_st7920_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) { uint8_t i, y; switch (msg) { case U8G_DEV_MSG_INIT: { OUT_WRITE(ST7920_CS_PIN, LOW); OUT_WRITE(ST7920_DAT_PIN, LOW); OUT_WRITE(ST7920_CLK_PIN, HIGH); ST7920_CS(); u8g_Delay(120); //initial delay for boot up ST7920_SET_CMD(); ST7920_WRITE_BYTE(0x20); //non-extended mode ST7920_WRITE_BYTE(0x08); //display off, cursor+blink off ST7920_WRITE_BYTE(0x01); //clear DDRAM ram u8g_Delay(15); //delay for DDRAM clear ST7920_WRITE_BYTE(0x24); //extended mode ST7920_WRITE_BYTE(0x26); //extended mode + GDRAM active for (y = 0; y < (LCD_PIXEL_HEIGHT) / 2; y++) { //clear GDRAM ST7920_WRITE_BYTE(0x80 | y); //set y ST7920_WRITE_BYTE(0x80); //set x = 0 ST7920_SET_DAT(); for (i = 0; i < 2 * (LCD_PIXEL_WIDTH) / 8; i++) //2x width clears both segments ST7920_WRITE_BYTE(0); ST7920_SET_CMD(); } ST7920_WRITE_BYTE(0x0C); //display on, cursor+blink off ST7920_NCS(); } break; case U8G_DEV_MSG_STOP: break; case U8G_DEV_MSG_PAGE_NEXT: { uint8_t* ptr; u8g_pb_t* pb = (u8g_pb_t*)(dev->dev_mem); y = pb->p.page_y0; ptr = (uint8_t*)pb->buf; ST7920_CS(); for (i = 0; i < PAGE_HEIGHT; i ++) { ST7920_SET_CMD(); if (y < 32) { ST7920_WRITE_BYTE(0x80 | y); //y ST7920_WRITE_BYTE(0x80); //x=0 } else { ST7920_WRITE_BYTE(0x80 | (y - 32)); //y ST7920_WRITE_BYTE(0x80 | 8); //x=64 } ST7920_SET_DAT(); ST7920_WRITE_BYTES(ptr, (LCD_PIXEL_WIDTH) / 8); //ptr is incremented inside of macro y++; } ST7920_NCS(); } break; } #if PAGE_HEIGHT == 8 return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg); #elif PAGE_HEIGHT == 16 return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg); #else return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg); #endif }