/*
* Primitive assembler breaks up adjacency primitives and assembles
* the base primitives they represent, e.g. vertices forming
* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
* become vertices forming PIPE_PRIM_TRIANGLES
* This is needed because specification says that the adjacency
* primitives are only visible in the geometry shader so we need
* to get rid of them so that the rest of the pipeline can
* process the inputs.
*/
void
draw_prim_assembler_run(struct draw_context *draw,
const struct draw_prim_info *input_prims,
const struct draw_vertex_info *input_verts,
struct draw_prim_info *output_prims,
struct draw_vertex_info *output_verts)
{
struct draw_assembler *asmblr = draw->ia;
unsigned start, i;
unsigned assembled_prim = u_reduced_prim(input_prims->prim);
unsigned max_primitives = u_decomposed_prims_for_vertices(
input_prims->prim, input_prims->count);
unsigned max_verts = u_vertices_per_prim(assembled_prim) * max_primitives;
asmblr->output_prims = output_prims;
asmblr->output_verts = output_verts;
asmblr->input_prims = input_prims;
asmblr->input_verts = input_verts;
asmblr->needs_primid = needs_primid(asmblr->draw);
asmblr->primid = 0;
asmblr->num_prims = 0;
output_prims->linear = TRUE;
output_prims->elts = NULL;
output_prims->start = 0;
output_prims->prim = assembled_prim;
output_prims->flags = 0x0;
output_prims->primitive_lengths = MALLOC(sizeof(unsigned));
output_prims->primitive_lengths[0] = 0;
output_prims->primitive_count = 1;
output_verts->vertex_size = input_verts->vertex_size;
output_verts->stride = input_verts->stride;
output_verts->verts = (struct vertex_header*)MALLOC(
input_verts->vertex_size * max_verts);
output_verts->count = 0;
for (start = i = 0; i < input_prims->primitive_count;
start += input_prims->primitive_lengths[i], i++)
{
unsigned count = input_prims->primitive_lengths[i];
if (input_prims->linear) {
assembler_run_linear(asmblr, input_prims, input_verts,
start, count);
} else {
assembler_run_elts(asmblr, input_prims, input_verts,
start, count);
}
}
output_prims->primitive_lengths[0] = output_verts->count;
output_prims->count = output_verts->count;
}
static boolean
iter_property(
struct tgsi_iterate_context *iter,
struct tgsi_full_property *prop )
{
struct sanity_check_ctx *ctx = (struct sanity_check_ctx *) iter;
if (iter->processor.Processor == TGSI_PROCESSOR_GEOMETRY &&
prop->Property.PropertyName == TGSI_PROPERTY_GS_INPUT_PRIM) {
ctx->implied_array_size = u_vertices_per_prim(prop->u[0].Data);
}
return TRUE;
}
static void
gen6_draw_gs(struct ilo_render *r,
const struct ilo_state_vector *vec,
struct ilo_render_draw_session *session)
{
/* 3DSTATE_CONSTANT_GS */
if (session->pcb_gs_changed)
gen6_3DSTATE_CONSTANT_GS(r->builder, NULL, NULL, 0);
/* 3DSTATE_GS */
if (DIRTY(GS) || DIRTY(VS) ||
session->prim_changed || r->instruction_bo_changed) {
if (vec->gs) {
gen6_3DSTATE_GS(r->builder, vec->gs);
} else if (vec->vs &&
ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_GEN6_SO)) {
const int verts_per_prim = u_vertices_per_prim(session->reduced_prim);
gen6_so_3DSTATE_GS(r->builder, vec->vs, verts_per_prim);
} else {
gen6_disable_3DSTATE_GS(r->builder);
}
}
}
/**
* Emit context states and 3DPRIMITIVE.
*/
bool
ilo_3d_pipeline_emit_draw(struct ilo_3d_pipeline *p,
const struct ilo_context *ilo,
int *prim_generated, int *prim_emitted)
{
bool success;
if (ilo->dirty & ILO_DIRTY_SO &&
ilo->so.enabled && !ilo->so.append_bitmask) {
/*
* We keep track of the SVBI in the driver, so that we can restore it
* when the HW context is invalidated (by another process). The value
* needs to be reset when stream output is enabled and the targets are
* changed.
*/
p->state.so_num_vertices = 0;
/* on GEN7+, we need SOL_RESET to reset the SO write offsets */
if (p->dev->gen >= ILO_GEN(7))
ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
}
while (true) {
struct ilo_builder_snapshot snapshot;
/* we will rewind if aperture check below fails */
ilo_builder_batch_snapshot(&p->cp->builder, &snapshot);
handle_invalid_batch_bo(p, false);
/* draw! */
p->emit_draw(p, ilo);
if (ilo_builder_validate(&ilo->cp->builder, 0, NULL)) {
success = true;
break;
}
/* rewind */
ilo_builder_batch_restore(&p->cp->builder, &snapshot);
if (ilo_cp_empty(p->cp)) {
success = false;
break;
}
else {
/* flush and try again */
ilo_cp_flush(p->cp, "out of aperture");
}
}
if (success) {
const int num_verts =
u_vertices_per_prim(u_reduced_prim(ilo->draw->mode));
const int max_emit =
(p->state.so_max_vertices - p->state.so_num_vertices) / num_verts;
const int generated =
u_reduced_prims_for_vertices(ilo->draw->mode, ilo->draw->count);
const int emitted = MIN2(generated, max_emit);
p->state.so_num_vertices += emitted * num_verts;
if (prim_generated)
*prim_generated = generated;
if (prim_emitted)
*prim_emitted = emitted;
}
p->invalidate_flags = 0x0;
return success;
}
/**
* Scan the given TGSI shader to collect information such as number of
* registers used, special instructions used, etc.
* \return info the result of the scan
*/
void
tgsi_scan_shader(const struct tgsi_token *tokens,
struct tgsi_shader_info *info)
{
uint procType, i;
struct tgsi_parse_context parse;
memset(info, 0, sizeof(*info));
for (i = 0; i < TGSI_FILE_COUNT; i++)
info->file_max[i] = -1;
/**
** Setup to begin parsing input shader
**/
if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
return;
}
procType = parse.FullHeader.Processor.Processor;
assert(procType == TGSI_PROCESSOR_FRAGMENT ||
procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY ||
procType == TGSI_PROCESSOR_COMPUTE);
info->processor = procType;
/**
** Loop over incoming program tokens/instructions
*/
while( !tgsi_parse_end_of_tokens( &parse ) ) {
info->num_tokens++;
tgsi_parse_token( &parse );
switch( parse.FullToken.Token.Type ) {
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
const struct tgsi_full_instruction *fullinst
= &parse.FullToken.FullInstruction;
uint i;
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
&fullinst->Src[i];
int ind = src->Register.Index;
/* Mark which inputs are effectively used */
if (src->Register.File == TGSI_FILE_INPUT) {
unsigned usage_mask;
usage_mask = tgsi_util_get_inst_usage_mask(fullinst, i);
if (src->Register.Indirect) {
for (ind = 0; ind < info->num_inputs; ++ind) {
info->input_usage_mask[ind] |= usage_mask;
}
} else {
assert(ind >= 0);
assert(ind < PIPE_MAX_SHADER_INPUTS);
info->input_usage_mask[ind] |= usage_mask;
}
if (procType == TGSI_PROCESSOR_FRAGMENT &&
src->Register.File == TGSI_FILE_INPUT &&
info->reads_position &&
src->Register.Index == 0 &&
(src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
src->Register.SwizzleW == TGSI_SWIZZLE_Z)) {
info->reads_z = TRUE;
}
}
/* check for indirect register reads */
if (src->Register.Indirect) {
info->indirect_files |= (1 << src->Register.File);
}
}
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
if (dst->Register.Indirect) {
info->indirect_files |= (1 << dst->Register.File);
}
}
info->num_instructions++;
}
break;
case TGSI_TOKEN_TYPE_DECLARATION:
{
const struct tgsi_full_declaration *fulldecl
= &parse.FullToken.FullDeclaration;
const uint file = fulldecl->Declaration.File;
uint reg;
for (reg = fulldecl->Range.First;
reg <= fulldecl->Range.Last;
reg++) {
/* only first 32 regs will appear in this bitfield */
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
if (file == TGSI_FILE_INPUT) {
info->input_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name;
info->input_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index;
info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
info->input_centroid[reg] = (ubyte)fulldecl->Interp.Centroid;
info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
info->num_inputs++;
if (procType == TGSI_PROCESSOR_FRAGMENT &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_POSITION)
info->reads_position = TRUE;
}
else if (file == TGSI_FILE_SYSTEM_VALUE) {
unsigned index = fulldecl->Range.First;
unsigned semName = fulldecl->Semantic.Name;
info->system_value_semantic_name[index] = semName;
info->num_system_values = MAX2(info->num_system_values,
index + 1);
/*
info->system_value_semantic_name[info->num_system_values++] =
fulldecl->Semantic.Name;
*/
if (fulldecl->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) {
info->uses_instanceid = TRUE;
}
else if (fulldecl->Semantic.Name == TGSI_SEMANTIC_VERTEXID) {
info->uses_vertexid = TRUE;
} else if (fulldecl->Semantic.Name == TGSI_SEMANTIC_PRIMID) {
info->uses_primid = TRUE;
}
}
else if (file == TGSI_FILE_OUTPUT) {
info->output_semantic_name[reg] = (ubyte)fulldecl->Semantic.Name;
info->output_semantic_index[reg] = (ubyte)fulldecl->Semantic.Index;
info->num_outputs++;
if ((procType == TGSI_PROCESSOR_VERTEX || procType == TGSI_PROCESSOR_GEOMETRY) &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_CLIPDIST) {
info->num_written_clipdistance += util_bitcount(fulldecl->Declaration.UsageMask);
}
if ((procType == TGSI_PROCESSOR_VERTEX || procType == TGSI_PROCESSOR_GEOMETRY) &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_CULLDIST) {
info->num_written_culldistance += util_bitcount(fulldecl->Declaration.UsageMask);
}
/* extra info for special outputs */
if (procType == TGSI_PROCESSOR_FRAGMENT &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_POSITION)
info->writes_z = TRUE;
if (procType == TGSI_PROCESSOR_FRAGMENT &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_STENCIL)
info->writes_stencil = TRUE;
if (procType == TGSI_PROCESSOR_VERTEX &&
fulldecl->Semantic.Name == TGSI_SEMANTIC_EDGEFLAG) {
info->writes_edgeflag = TRUE;
}
if (procType == TGSI_PROCESSOR_GEOMETRY &&
fulldecl->Semantic.Name ==
TGSI_SEMANTIC_VIEWPORT_INDEX) {
info->writes_viewport_index = TRUE;
}
if (procType == TGSI_PROCESSOR_GEOMETRY &&
fulldecl->Semantic.Name ==
TGSI_SEMANTIC_LAYER) {
info->writes_layer = TRUE;
}
}
}
}
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
{
uint reg = info->immediate_count++;
uint file = TGSI_FILE_IMMEDIATE;
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
}
break;
case TGSI_TOKEN_TYPE_PROPERTY:
{
const struct tgsi_full_property *fullprop
= &parse.FullToken.FullProperty;
info->properties[info->num_properties].name =
fullprop->Property.PropertyName;
memcpy(info->properties[info->num_properties].data,
fullprop->u, 8 * sizeof(unsigned));;
++info->num_properties;
}
break;
default:
assert( 0 );
}
}
info->uses_kill = (info->opcode_count[TGSI_OPCODE_KIL] ||
info->opcode_count[TGSI_OPCODE_KILP]);
/* extract simple properties */
for (i = 0; i < info->num_properties; ++i) {
switch (info->properties[i].name) {
case TGSI_PROPERTY_FS_COORD_ORIGIN:
info->origin_lower_left = info->properties[i].data[0];
break;
case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
info->pixel_center_integer = info->properties[i].data[0];
break;
case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
info->color0_writes_all_cbufs = info->properties[i].data[0];
break;
case TGSI_PROPERTY_GS_INPUT_PRIM:
/* The dimensions of the IN decleration in geometry shader have
* to be deduced from the type of the input primitive.
*/
if (procType == TGSI_PROCESSOR_GEOMETRY) {
unsigned input_primitive = info->properties[i].data[0];
int num_verts = u_vertices_per_prim(input_primitive);
unsigned j;
info->file_count[TGSI_FILE_INPUT] = num_verts;
info->file_max[TGSI_FILE_INPUT] =
MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
for (j = 0; j < num_verts; ++j) {
info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
}
}
break;
default:
;
}
}
tgsi_parse_free (&parse);
}
static boolean parse_property( struct translate_ctx *ctx )
{
struct tgsi_full_property prop;
uint property_name;
uint values[8];
uint advance;
char id[64];
if (!eat_white( &ctx->cur )) {
report_error( ctx, "Syntax error" );
return FALSE;
}
if (!parse_identifier( &ctx->cur, id )) {
report_error( ctx, "Syntax error" );
return FALSE;
}
for (property_name = 0; property_name < TGSI_PROPERTY_COUNT;
++property_name) {
if (streq_nocase_uprcase(tgsi_property_names[property_name], id)) {
break;
}
}
if (property_name >= TGSI_PROPERTY_COUNT) {
debug_printf( "\nError: Unknown property : '%s'", id );
return FALSE;
}
eat_opt_white( &ctx->cur );
switch(property_name) {
case TGSI_PROPERTY_GS_INPUT_PRIM:
case TGSI_PROPERTY_GS_OUTPUT_PRIM:
if (!parse_primitive(&ctx->cur, &values[0] )) {
report_error( ctx, "Unknown primitive name as property!" );
return FALSE;
}
if (property_name == TGSI_PROPERTY_GS_INPUT_PRIM &&
ctx->processor == TGSI_PROCESSOR_GEOMETRY) {
ctx->implied_array_size = u_vertices_per_prim(values[0]);
}
break;
case TGSI_PROPERTY_FS_COORD_ORIGIN:
if (!parse_fs_coord_origin(&ctx->cur, &values[0] )) {
report_error( ctx, "Unknown coord origin as property: must be UPPER_LEFT or LOWER_LEFT!" );
return FALSE;
}
break;
case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
if (!parse_fs_coord_pixel_center(&ctx->cur, &values[0] )) {
report_error( ctx, "Unknown coord pixel center as property: must be HALF_INTEGER or INTEGER!" );
return FALSE;
}
break;
case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
default:
if (!parse_uint(&ctx->cur, &values[0] )) {
report_error( ctx, "Expected unsigned integer as property!" );
return FALSE;
}
}
prop = tgsi_default_full_property();
prop.Property.PropertyName = property_name;
prop.Property.NrTokens += 1;
prop.u[0].Data = values[0];
advance = tgsi_build_full_property(
&prop,
ctx->tokens_cur,
ctx->header,
(uint) (ctx->tokens_end - ctx->tokens_cur) );
if (advance == 0)
return FALSE;
ctx->tokens_cur += advance;
return TRUE;
}
/*
* Draw vertex arrays, with optional indexing, optional instancing.
*/
static void
swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
{
struct swr_context *ctx = swr_context(pipe);
if (!swr_check_render_cond(pipe))
return;
if (info->indirect) {
util_draw_indirect(pipe, info);
return;
}
/* Update derived state, pass draw info to update function */
if (ctx->dirty)
swr_update_derived(pipe, info);
swr_update_draw_context(ctx);
if (ctx->vs->pipe.stream_output.num_outputs) {
if (!ctx->vs->soFunc[info->mode]) {
STREAMOUT_COMPILE_STATE state = {0};
struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
state.numVertsPerPrim = u_vertices_per_prim(info->mode);
uint32_t offsets[MAX_SO_STREAMS] = {0};
uint32_t num = 0;
for (uint32_t i = 0; i < so->num_outputs; i++) {
assert(so->output[i].stream == 0); // @todo
uint32_t output_buffer = so->output[i].output_buffer;
if (so->output[i].dst_offset != offsets[output_buffer]) {
// hole - need to fill
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].hole = true;
state.stream.decl[num].componentMask =
(1 << (so->output[i].dst_offset - offsets[output_buffer]))
- 1;
num++;
offsets[output_buffer] = so->output[i].dst_offset;
}
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].attribSlot = so->output[i].register_index - 1;
state.stream.decl[num].componentMask =
((1 << so->output[i].num_components) - 1)
<< so->output[i].start_component;
state.stream.decl[num].hole = false;
num++;
offsets[output_buffer] += so->output[i].num_components;
}
state.stream.numDecls = num;
HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
debug_printf("so shader %p\n", ctx->vs->soFunc[info->mode]);
assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
}
SwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
}
struct swr_vertex_element_state *velems = ctx->velems;
if (!velems->fsFunc
|| (velems->fsState.cutIndex != info->restart_index)
|| (velems->fsState.bEnableCutIndex != info->primitive_restart)) {
velems->fsState.cutIndex = info->restart_index;
velems->fsState.bEnableCutIndex = info->primitive_restart;
/* Create Fetch Shader */
HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
debug_printf("fetch shader %p\n", velems->fsFunc);
assert(velems->fsFunc && "Error: FetchShader = NULL");
}
SwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
/* Set up frontend state
* XXX setup provokingVertex & topologyProvokingVertex */
SWR_FRONTEND_STATE feState = {0};
if (ctx->rasterizer->flatshade_first) {
feState.provokingVertex = {1, 0, 0};
} else {
feState.provokingVertex = {2, 1, 2};
}
switch (info->mode) {
case PIPE_PRIM_TRIANGLE_FAN:
feState.topologyProvokingVertex = feState.provokingVertex.triFan;
break;
case PIPE_PRIM_TRIANGLE_STRIP:
case PIPE_PRIM_TRIANGLES:
feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
break;
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_QUADS:
if (ctx->rasterizer->flatshade_first)
feState.topologyProvokingVertex = 0;
else
feState.topologyProvokingVertex = 3;
break;
case PIPE_PRIM_LINES:
case PIPE_PRIM_LINE_LOOP:
case PIPE_PRIM_LINE_STRIP:
feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
break;
default:
feState.topologyProvokingVertex = 0;
}
feState.bEnableCutIndex = info->primitive_restart;
SwrSetFrontendState(ctx->swrContext, &feState);
if (info->indexed)
SwrDrawIndexedInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->index_bias,
info->start_instance);
else
SwrDrawInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->start_instance);
}
/**
* Scan the given TGSI shader to collect information such as number of
* registers used, special instructions used, etc.
* \return info the result of the scan
*/
void
tgsi_scan_shader(const struct tgsi_token *tokens,
struct tgsi_shader_info *info)
{
uint procType, i;
struct tgsi_parse_context parse;
unsigned current_depth = 0;
memset(info, 0, sizeof(*info));
for (i = 0; i < TGSI_FILE_COUNT; i++)
info->file_max[i] = -1;
for (i = 0; i < ARRAY_SIZE(info->const_file_max); i++)
info->const_file_max[i] = -1;
info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
for (i = 0; i < ARRAY_SIZE(info->sampler_targets); i++)
info->sampler_targets[i] = TGSI_TEXTURE_UNKNOWN;
/**
** Setup to begin parsing input shader
**/
if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
return;
}
procType = parse.FullHeader.Processor.Processor;
assert(procType == PIPE_SHADER_FRAGMENT ||
procType == PIPE_SHADER_VERTEX ||
procType == PIPE_SHADER_GEOMETRY ||
procType == PIPE_SHADER_TESS_CTRL ||
procType == PIPE_SHADER_TESS_EVAL ||
procType == PIPE_SHADER_COMPUTE);
info->processor = procType;
/**
** Loop over incoming program tokens/instructions
*/
while (!tgsi_parse_end_of_tokens(&parse)) {
info->num_tokens++;
tgsi_parse_token( &parse );
switch( parse.FullToken.Token.Type ) {
case TGSI_TOKEN_TYPE_INSTRUCTION:
scan_instruction(info, &parse.FullToken.FullInstruction,
¤t_depth);
break;
case TGSI_TOKEN_TYPE_DECLARATION:
scan_declaration(info, &parse.FullToken.FullDeclaration);
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
scan_immediate(info);
break;
case TGSI_TOKEN_TYPE_PROPERTY:
scan_property(info, &parse.FullToken.FullProperty);
break;
default:
assert(!"Unexpected TGSI token type");
}
}
info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
info->opcode_count[TGSI_OPCODE_KILL]);
/* The dimensions of the IN decleration in geometry shader have
* to be deduced from the type of the input primitive.
*/
if (procType == PIPE_SHADER_GEOMETRY) {
unsigned input_primitive =
info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
int num_verts = u_vertices_per_prim(input_primitive);
int j;
info->file_count[TGSI_FILE_INPUT] = num_verts;
info->file_max[TGSI_FILE_INPUT] =
MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
for (j = 0; j < num_verts; ++j) {
info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
}
}
tgsi_parse_free(&parse);
}
/**
* Scan the given TGSI shader to collect information such as number of
* registers used, special instructions used, etc.
* \return info the result of the scan
*/
void
tgsi_scan_shader(const struct tgsi_token *tokens,
struct tgsi_shader_info *info)
{
uint procType, i;
struct tgsi_parse_context parse;
memset(info, 0, sizeof(*info));
for (i = 0; i < TGSI_FILE_COUNT; i++)
info->file_max[i] = -1;
for (i = 0; i < Elements(info->const_file_max); i++)
info->const_file_max[i] = -1;
/**
** Setup to begin parsing input shader
**/
if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
return;
}
procType = parse.FullHeader.Processor.Processor;
assert(procType == TGSI_PROCESSOR_FRAGMENT ||
procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY ||
procType == TGSI_PROCESSOR_COMPUTE);
info->processor = procType;
/**
** Loop over incoming program tokens/instructions
*/
while( !tgsi_parse_end_of_tokens( &parse ) ) {
info->num_tokens++;
tgsi_parse_token( &parse );
switch( parse.FullToken.Token.Type ) {
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
const struct tgsi_full_instruction *fullinst
= &parse.FullToken.FullInstruction;
uint i;
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
&fullinst->Src[i];
int ind = src->Register.Index;
/* Mark which inputs are effectively used */
if (src->Register.File == TGSI_FILE_INPUT) {
unsigned usage_mask;
usage_mask = tgsi_util_get_inst_usage_mask(fullinst, i);
if (src->Register.Indirect) {
for (ind = 0; ind < info->num_inputs; ++ind) {
info->input_usage_mask[ind] |= usage_mask;
}
} else {
assert(ind >= 0);
assert(ind < PIPE_MAX_SHADER_INPUTS);
info->input_usage_mask[ind] |= usage_mask;
}
if (procType == TGSI_PROCESSOR_FRAGMENT &&
info->reads_position &&
src->Register.Index == 0 &&
(src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
src->Register.SwizzleW == TGSI_SWIZZLE_Z)) {
info->reads_z = TRUE;
}
}
/* check for indirect register reads */
if (src->Register.Indirect) {
info->indirect_files |= (1 << src->Register.File);
}
/* MSAA samplers */
if (src->Register.File == TGSI_FILE_SAMPLER) {
assert(fullinst->Instruction.Texture);
assert(src->Register.Index < Elements(info->is_msaa_sampler));
if (fullinst->Instruction.Texture &&
(fullinst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
fullinst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
info->is_msaa_sampler[src->Register.Index] = TRUE;
}
}
}
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
if (dst->Register.Indirect) {
info->indirect_files |= (1 << dst->Register.File);
}
}
info->num_instructions++;
}
break;
case TGSI_TOKEN_TYPE_DECLARATION:
{
const struct tgsi_full_declaration *fulldecl
= &parse.FullToken.FullDeclaration;
const uint file = fulldecl->Declaration.File;
uint reg;
for (reg = fulldecl->Range.First;
reg <= fulldecl->Range.Last;
reg++) {
unsigned semName = fulldecl->Semantic.Name;
unsigned semIndex = fulldecl->Semantic.Index;
/* only first 32 regs will appear in this bitfield */
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
if (file == TGSI_FILE_CONSTANT) {
int buffer = 0;
if (fulldecl->Declaration.Dimension)
buffer = fulldecl->Dim.Index2D;
info->const_file_max[buffer] =
MAX2(info->const_file_max[buffer], (int)reg);
}
else if (file == TGSI_FILE_INPUT) {
info->input_semantic_name[reg] = (ubyte) semName;
info->input_semantic_index[reg] = (ubyte) semIndex;
info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
info->num_inputs++;
if (semName == TGSI_SEMANTIC_PRIMID)
info->uses_primid = TRUE;
else if (procType == TGSI_PROCESSOR_FRAGMENT) {
if (semName == TGSI_SEMANTIC_POSITION)
info->reads_position = TRUE;
else if (semName == TGSI_SEMANTIC_FACE)
info->uses_frontface = TRUE;
}
}
else if (file == TGSI_FILE_SYSTEM_VALUE) {
unsigned index = fulldecl->Range.First;
info->system_value_semantic_name[index] = semName;
info->num_system_values = MAX2(info->num_system_values,
index + 1);
if (semName == TGSI_SEMANTIC_INSTANCEID) {
info->uses_instanceid = TRUE;
}
else if (semName == TGSI_SEMANTIC_VERTEXID) {
info->uses_vertexid = TRUE;
}
else if (semName == TGSI_SEMANTIC_PRIMID) {
info->uses_primid = TRUE;
}
}
else if (file == TGSI_FILE_OUTPUT) {
info->output_semantic_name[reg] = (ubyte) semName;
info->output_semantic_index[reg] = (ubyte) semIndex;
info->num_outputs++;
if (procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY) {
if (semName == TGSI_SEMANTIC_CLIPDIST) {
info->num_written_clipdistance +=
util_bitcount(fulldecl->Declaration.UsageMask);
}
else if (semName == TGSI_SEMANTIC_CULLDIST) {
info->num_written_culldistance +=
util_bitcount(fulldecl->Declaration.UsageMask);
}
}
if (procType == TGSI_PROCESSOR_FRAGMENT) {
if (semName == TGSI_SEMANTIC_POSITION) {
info->writes_z = TRUE;
}
else if (semName == TGSI_SEMANTIC_STENCIL) {
info->writes_stencil = TRUE;
}
}
if (procType == TGSI_PROCESSOR_VERTEX) {
if (semName == TGSI_SEMANTIC_EDGEFLAG) {
info->writes_edgeflag = TRUE;
}
}
if (procType == TGSI_PROCESSOR_GEOMETRY) {
if (semName == TGSI_SEMANTIC_VIEWPORT_INDEX) {
info->writes_viewport_index = TRUE;
}
else if (semName == TGSI_SEMANTIC_LAYER) {
info->writes_layer = TRUE;
}
}
}
}
}
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
{
uint reg = info->immediate_count++;
uint file = TGSI_FILE_IMMEDIATE;
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
}
break;
case TGSI_TOKEN_TYPE_PROPERTY:
{
const struct tgsi_full_property *fullprop
= &parse.FullToken.FullProperty;
unsigned name = fullprop->Property.PropertyName;
assert(name < Elements(info->properties));
info->properties[name] = fullprop->u[0].Data;
}
break;
default:
assert( 0 );
}
}
info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
info->opcode_count[TGSI_OPCODE_KILL]);
/* The dimensions of the IN decleration in geometry shader have
* to be deduced from the type of the input primitive.
*/
if (procType == TGSI_PROCESSOR_GEOMETRY) {
unsigned input_primitive =
info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
int num_verts = u_vertices_per_prim(input_primitive);
int j;
info->file_count[TGSI_FILE_INPUT] = num_verts;
info->file_max[TGSI_FILE_INPUT] =
MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
for (j = 0; j < num_verts; ++j) {
info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
}
}
tgsi_parse_free (&parse);
}
/**
* Scan the given TGSI shader to collect information such as number of
* registers used, special instructions used, etc.
* \return info the result of the scan
*/
void
tgsi_scan_shader(const struct tgsi_token *tokens,
struct tgsi_shader_info *info)
{
uint procType, i;
struct tgsi_parse_context parse;
unsigned current_depth = 0;
memset(info, 0, sizeof(*info));
for (i = 0; i < TGSI_FILE_COUNT; i++)
info->file_max[i] = -1;
for (i = 0; i < Elements(info->const_file_max); i++)
info->const_file_max[i] = -1;
info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = 1;
/**
** Setup to begin parsing input shader
**/
if (tgsi_parse_init( &parse, tokens ) != TGSI_PARSE_OK) {
debug_printf("tgsi_parse_init() failed in tgsi_scan_shader()!\n");
return;
}
procType = parse.FullHeader.Processor.Processor;
assert(procType == TGSI_PROCESSOR_FRAGMENT ||
procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY ||
procType == TGSI_PROCESSOR_TESS_CTRL ||
procType == TGSI_PROCESSOR_TESS_EVAL ||
procType == TGSI_PROCESSOR_COMPUTE);
info->processor = procType;
/**
** Loop over incoming program tokens/instructions
*/
while( !tgsi_parse_end_of_tokens( &parse ) ) {
info->num_tokens++;
tgsi_parse_token( &parse );
switch( parse.FullToken.Token.Type ) {
case TGSI_TOKEN_TYPE_INSTRUCTION:
{
const struct tgsi_full_instruction *fullinst
= &parse.FullToken.FullInstruction;
uint i;
assert(fullinst->Instruction.Opcode < TGSI_OPCODE_LAST);
info->opcode_count[fullinst->Instruction.Opcode]++;
switch (fullinst->Instruction.Opcode) {
case TGSI_OPCODE_IF:
case TGSI_OPCODE_UIF:
case TGSI_OPCODE_BGNLOOP:
current_depth++;
info->max_depth = MAX2(info->max_depth, current_depth);
break;
case TGSI_OPCODE_ENDIF:
case TGSI_OPCODE_ENDLOOP:
current_depth--;
break;
default:
break;
}
if (fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID ||
fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
fullinst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
const struct tgsi_full_src_register *src0 = &fullinst->Src[0];
unsigned input;
if (src0->Register.Indirect && src0->Indirect.ArrayID)
input = info->input_array_first[src0->Indirect.ArrayID];
else
input = src0->Register.Index;
/* For the INTERP opcodes, the interpolation is always
* PERSPECTIVE unless LINEAR is specified.
*/
switch (info->input_interpolate[input]) {
case TGSI_INTERPOLATE_COLOR:
case TGSI_INTERPOLATE_CONSTANT:
case TGSI_INTERPOLATE_PERSPECTIVE:
switch (fullinst->Instruction.Opcode) {
case TGSI_OPCODE_INTERP_CENTROID:
info->uses_persp_opcode_interp_centroid = true;
break;
case TGSI_OPCODE_INTERP_OFFSET:
info->uses_persp_opcode_interp_offset = true;
break;
case TGSI_OPCODE_INTERP_SAMPLE:
info->uses_persp_opcode_interp_sample = true;
break;
}
break;
case TGSI_INTERPOLATE_LINEAR:
switch (fullinst->Instruction.Opcode) {
case TGSI_OPCODE_INTERP_CENTROID:
info->uses_linear_opcode_interp_centroid = true;
break;
case TGSI_OPCODE_INTERP_OFFSET:
info->uses_linear_opcode_interp_offset = true;
break;
case TGSI_OPCODE_INTERP_SAMPLE:
info->uses_linear_opcode_interp_sample = true;
break;
}
break;
}
}
if (fullinst->Instruction.Opcode >= TGSI_OPCODE_F2D &&
fullinst->Instruction.Opcode <= TGSI_OPCODE_DSSG)
info->uses_doubles = true;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
&fullinst->Src[i];
int ind = src->Register.Index;
/* Mark which inputs are effectively used */
if (src->Register.File == TGSI_FILE_INPUT) {
unsigned usage_mask;
usage_mask = tgsi_util_get_inst_usage_mask(fullinst, i);
if (src->Register.Indirect) {
for (ind = 0; ind < info->num_inputs; ++ind) {
info->input_usage_mask[ind] |= usage_mask;
}
} else {
assert(ind >= 0);
assert(ind < PIPE_MAX_SHADER_INPUTS);
info->input_usage_mask[ind] |= usage_mask;
}
if (procType == TGSI_PROCESSOR_FRAGMENT &&
!src->Register.Indirect) {
unsigned name =
info->input_semantic_name[src->Register.Index];
unsigned index =
info->input_semantic_index[src->Register.Index];
if (name == TGSI_SEMANTIC_POSITION &&
(src->Register.SwizzleX == TGSI_SWIZZLE_Z ||
src->Register.SwizzleY == TGSI_SWIZZLE_Z ||
src->Register.SwizzleZ == TGSI_SWIZZLE_Z ||
src->Register.SwizzleW == TGSI_SWIZZLE_Z))
info->reads_z = TRUE;
if (name == TGSI_SEMANTIC_COLOR) {
unsigned mask =
(1 << src->Register.SwizzleX) |
(1 << src->Register.SwizzleY) |
(1 << src->Register.SwizzleZ) |
(1 << src->Register.SwizzleW);
info->colors_read |= mask << (index * 4);
}
}
}
/* check for indirect register reads */
if (src->Register.Indirect) {
info->indirect_files |= (1 << src->Register.File);
info->indirect_files_read |= (1 << src->Register.File);
}
/* MSAA samplers */
if (src->Register.File == TGSI_FILE_SAMPLER) {
assert(fullinst->Instruction.Texture);
assert(src->Register.Index < Elements(info->is_msaa_sampler));
if (fullinst->Instruction.Texture &&
(fullinst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
fullinst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
info->is_msaa_sampler[src->Register.Index] = TRUE;
}
}
}
/* check for indirect register writes */
for (i = 0; i < fullinst->Instruction.NumDstRegs; i++) {
const struct tgsi_full_dst_register *dst = &fullinst->Dst[i];
if (dst->Register.Indirect) {
info->indirect_files |= (1 << dst->Register.File);
info->indirect_files_written |= (1 << dst->Register.File);
}
}
info->num_instructions++;
}
break;
case TGSI_TOKEN_TYPE_DECLARATION:
{
const struct tgsi_full_declaration *fulldecl
= &parse.FullToken.FullDeclaration;
const uint file = fulldecl->Declaration.File;
uint reg;
if (fulldecl->Declaration.Array) {
unsigned array_id = fulldecl->Array.ArrayID;
switch (file) {
case TGSI_FILE_INPUT:
assert(array_id < ARRAY_SIZE(info->input_array_first));
info->input_array_first[array_id] = fulldecl->Range.First;
info->input_array_last[array_id] = fulldecl->Range.Last;
break;
case TGSI_FILE_OUTPUT:
assert(array_id < ARRAY_SIZE(info->output_array_first));
info->output_array_first[array_id] = fulldecl->Range.First;
info->output_array_last[array_id] = fulldecl->Range.Last;
break;
}
info->array_max[file] = MAX2(info->array_max[file], array_id);
}
for (reg = fulldecl->Range.First;
reg <= fulldecl->Range.Last;
reg++) {
unsigned semName = fulldecl->Semantic.Name;
unsigned semIndex =
fulldecl->Semantic.Index + (reg - fulldecl->Range.First);
/* only first 32 regs will appear in this bitfield */
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
if (file == TGSI_FILE_CONSTANT) {
int buffer = 0;
if (fulldecl->Declaration.Dimension)
buffer = fulldecl->Dim.Index2D;
info->const_file_max[buffer] =
MAX2(info->const_file_max[buffer], (int)reg);
}
else if (file == TGSI_FILE_INPUT) {
info->input_semantic_name[reg] = (ubyte) semName;
info->input_semantic_index[reg] = (ubyte) semIndex;
info->input_interpolate[reg] = (ubyte)fulldecl->Interp.Interpolate;
info->input_interpolate_loc[reg] = (ubyte)fulldecl->Interp.Location;
info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap;
info->num_inputs++;
/* Only interpolated varyings. Don't include POSITION.
* Don't include integer varyings, because they are not
* interpolated.
*/
if (semName == TGSI_SEMANTIC_GENERIC ||
semName == TGSI_SEMANTIC_TEXCOORD ||
semName == TGSI_SEMANTIC_COLOR ||
semName == TGSI_SEMANTIC_BCOLOR ||
semName == TGSI_SEMANTIC_FOG ||
semName == TGSI_SEMANTIC_CLIPDIST ||
semName == TGSI_SEMANTIC_CULLDIST) {
switch (fulldecl->Interp.Interpolate) {
case TGSI_INTERPOLATE_COLOR:
case TGSI_INTERPOLATE_PERSPECTIVE:
switch (fulldecl->Interp.Location) {
case TGSI_INTERPOLATE_LOC_CENTER:
info->uses_persp_center = true;
break;
case TGSI_INTERPOLATE_LOC_CENTROID:
info->uses_persp_centroid = true;
break;
case TGSI_INTERPOLATE_LOC_SAMPLE:
info->uses_persp_sample = true;
break;
}
break;
case TGSI_INTERPOLATE_LINEAR:
switch (fulldecl->Interp.Location) {
case TGSI_INTERPOLATE_LOC_CENTER:
info->uses_linear_center = true;
break;
case TGSI_INTERPOLATE_LOC_CENTROID:
info->uses_linear_centroid = true;
break;
case TGSI_INTERPOLATE_LOC_SAMPLE:
info->uses_linear_sample = true;
break;
}
break;
/* TGSI_INTERPOLATE_CONSTANT doesn't do any interpolation. */
}
}
if (semName == TGSI_SEMANTIC_PRIMID)
info->uses_primid = TRUE;
else if (procType == TGSI_PROCESSOR_FRAGMENT) {
if (semName == TGSI_SEMANTIC_POSITION)
info->reads_position = TRUE;
else if (semName == TGSI_SEMANTIC_FACE)
info->uses_frontface = TRUE;
}
}
else if (file == TGSI_FILE_SYSTEM_VALUE) {
unsigned index = fulldecl->Range.First;
info->system_value_semantic_name[index] = semName;
info->num_system_values = MAX2(info->num_system_values,
index + 1);
if (semName == TGSI_SEMANTIC_INSTANCEID) {
info->uses_instanceid = TRUE;
}
else if (semName == TGSI_SEMANTIC_VERTEXID) {
info->uses_vertexid = TRUE;
}
else if (semName == TGSI_SEMANTIC_VERTEXID_NOBASE) {
info->uses_vertexid_nobase = TRUE;
}
else if (semName == TGSI_SEMANTIC_BASEVERTEX) {
info->uses_basevertex = TRUE;
}
else if (semName == TGSI_SEMANTIC_PRIMID) {
info->uses_primid = TRUE;
} else if (semName == TGSI_SEMANTIC_INVOCATIONID) {
info->uses_invocationid = TRUE;
}
}
else if (file == TGSI_FILE_OUTPUT) {
info->output_semantic_name[reg] = (ubyte) semName;
info->output_semantic_index[reg] = (ubyte) semIndex;
info->num_outputs++;
if (semName == TGSI_SEMANTIC_COLOR)
info->colors_written |= 1 << semIndex;
if (procType == TGSI_PROCESSOR_VERTEX ||
procType == TGSI_PROCESSOR_GEOMETRY ||
procType == TGSI_PROCESSOR_TESS_CTRL ||
procType == TGSI_PROCESSOR_TESS_EVAL) {
if (semName == TGSI_SEMANTIC_VIEWPORT_INDEX) {
info->writes_viewport_index = TRUE;
}
else if (semName == TGSI_SEMANTIC_LAYER) {
info->writes_layer = TRUE;
}
else if (semName == TGSI_SEMANTIC_PSIZE) {
info->writes_psize = TRUE;
}
else if (semName == TGSI_SEMANTIC_CLIPVERTEX) {
info->writes_clipvertex = TRUE;
}
}
if (procType == TGSI_PROCESSOR_FRAGMENT) {
if (semName == TGSI_SEMANTIC_POSITION) {
info->writes_z = TRUE;
}
else if (semName == TGSI_SEMANTIC_STENCIL) {
info->writes_stencil = TRUE;
} else if (semName == TGSI_SEMANTIC_SAMPLEMASK) {
info->writes_samplemask = TRUE;
}
}
if (procType == TGSI_PROCESSOR_VERTEX) {
if (semName == TGSI_SEMANTIC_EDGEFLAG) {
info->writes_edgeflag = TRUE;
}
}
} else if (file == TGSI_FILE_SAMPLER) {
info->samplers_declared |= 1 << reg;
}
}
}
break;
case TGSI_TOKEN_TYPE_IMMEDIATE:
{
uint reg = info->immediate_count++;
uint file = TGSI_FILE_IMMEDIATE;
info->file_mask[file] |= (1 << reg);
info->file_count[file]++;
info->file_max[file] = MAX2(info->file_max[file], (int)reg);
}
break;
case TGSI_TOKEN_TYPE_PROPERTY:
{
const struct tgsi_full_property *fullprop
= &parse.FullToken.FullProperty;
unsigned name = fullprop->Property.PropertyName;
unsigned value = fullprop->u[0].Data;
assert(name < Elements(info->properties));
info->properties[name] = value;
switch (name) {
case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
info->num_written_clipdistance = value;
info->clipdist_writemask |= (1 << value) - 1;
break;
case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
info->num_written_culldistance = value;
info->culldist_writemask |= (1 << value) - 1;
break;
}
}
break;
default:
assert( 0 );
}
}
info->uses_kill = (info->opcode_count[TGSI_OPCODE_KILL_IF] ||
info->opcode_count[TGSI_OPCODE_KILL]);
/* The dimensions of the IN decleration in geometry shader have
* to be deduced from the type of the input primitive.
*/
if (procType == TGSI_PROCESSOR_GEOMETRY) {
unsigned input_primitive =
info->properties[TGSI_PROPERTY_GS_INPUT_PRIM];
int num_verts = u_vertices_per_prim(input_primitive);
int j;
info->file_count[TGSI_FILE_INPUT] = num_verts;
info->file_max[TGSI_FILE_INPUT] =
MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
for (j = 0; j < num_verts; ++j) {
info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
}
}
tgsi_parse_free (&parse);
}
/*
* Draw vertex arrays, with optional indexing, optional instancing.
*/
static void
swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
{
struct swr_context *ctx = swr_context(pipe);
if (!info->count_from_stream_output && !info->indirect &&
!info->primitive_restart &&
!u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
return;
if (!swr_check_render_cond(pipe))
return;
if (info->indirect) {
util_draw_indirect(pipe, info);
return;
}
/* If indexed draw, force vertex validation since index buffer comes
* from draw info. */
if (info->index_size)
ctx->dirty |= SWR_NEW_VERTEX;
/* Update derived state, pass draw info to update function. */
swr_update_derived(pipe, info);
swr_update_draw_context(ctx);
if (ctx->vs->pipe.stream_output.num_outputs) {
if (!ctx->vs->soFunc[info->mode]) {
STREAMOUT_COMPILE_STATE state = {0};
struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
state.numVertsPerPrim = u_vertices_per_prim(info->mode);
uint32_t offsets[MAX_SO_STREAMS] = {0};
uint32_t num = 0;
for (uint32_t i = 0; i < so->num_outputs; i++) {
assert(so->output[i].stream == 0); // @todo
uint32_t output_buffer = so->output[i].output_buffer;
if (so->output[i].dst_offset != offsets[output_buffer]) {
// hole - need to fill
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].hole = true;
state.stream.decl[num].componentMask =
(1 << (so->output[i].dst_offset - offsets[output_buffer]))
- 1;
num++;
offsets[output_buffer] = so->output[i].dst_offset;
}
unsigned attrib_slot = so->output[i].register_index;
attrib_slot = swr_so_adjust_attrib(attrib_slot, ctx->vs);
state.stream.decl[num].bufferIndex = output_buffer;
state.stream.decl[num].attribSlot = attrib_slot;
state.stream.decl[num].componentMask =
((1 << so->output[i].num_components) - 1)
<< so->output[i].start_component;
state.stream.decl[num].hole = false;
num++;
offsets[output_buffer] += so->output[i].num_components;
}
state.stream.numDecls = num;
HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
debug_printf("so shader %p\n", ctx->vs->soFunc[info->mode]);
assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
}
ctx->api.pfnSwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
}
struct swr_vertex_element_state *velems = ctx->velems;
if (info->primitive_restart)
velems->fsState.cutIndex = info->restart_index;
else
velems->fsState.cutIndex = 0;
velems->fsState.bEnableCutIndex = info->primitive_restart;
velems->fsState.bPartialVertexBuffer = (info->min_index > 0);
swr_jit_fetch_key key;
swr_generate_fetch_key(key, velems);
auto search = velems->map.find(key);
if (search != velems->map.end()) {
velems->fsFunc = search->second;
} else {
HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
debug_printf("fetch shader %p\n", velems->fsFunc);
assert(velems->fsFunc && "Error: FetchShader = NULL");
velems->map.insert(std::make_pair(key, velems->fsFunc));
}
ctx->api.pfnSwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
/* Set up frontend state
* XXX setup provokingVertex & topologyProvokingVertex */
SWR_FRONTEND_STATE feState = {0};
// feState.vsVertexSize seeds the PA size that is used as an interface
// between all the shader stages, so it has to be large enough to
// incorporate all interfaces between stages
// max of gs and vs num_outputs
feState.vsVertexSize = ctx->vs->info.base.num_outputs;
if (ctx->gs &&
ctx->gs->info.base.num_outputs > feState.vsVertexSize) {
feState.vsVertexSize = ctx->gs->info.base.num_outputs;
}
if (ctx->vs->info.base.num_outputs) {
// gs does not adjust for position in SGV slot at input from vs
if (!ctx->gs)
feState.vsVertexSize--;
}
// other (non-SGV) slots start at VERTEX_ATTRIB_START_SLOT
feState.vsVertexSize += VERTEX_ATTRIB_START_SLOT;
// The PA in the clipper does not handle BE vertex sizes
// different from FE. Increase vertexsize only for the cases that needed it
// primid needs a slot
if (ctx->fs->info.base.uses_primid)
feState.vsVertexSize++;
// sprite coord enable
if (ctx->rasterizer->sprite_coord_enable)
feState.vsVertexSize++;
if (ctx->rasterizer->flatshade_first) {
feState.provokingVertex = {1, 0, 0};
} else {
feState.provokingVertex = {2, 1, 2};
}
enum pipe_prim_type topology;
if (ctx->gs)
topology = (pipe_prim_type)ctx->gs->info.base.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
else
topology = info->mode;
switch (topology) {
case PIPE_PRIM_TRIANGLE_FAN:
feState.topologyProvokingVertex = feState.provokingVertex.triFan;
break;
case PIPE_PRIM_TRIANGLE_STRIP:
case PIPE_PRIM_TRIANGLES:
feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
break;
case PIPE_PRIM_QUAD_STRIP:
case PIPE_PRIM_QUADS:
if (ctx->rasterizer->flatshade_first)
feState.topologyProvokingVertex = 0;
else
feState.topologyProvokingVertex = 3;
break;
case PIPE_PRIM_LINES:
case PIPE_PRIM_LINE_LOOP:
case PIPE_PRIM_LINE_STRIP:
feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
break;
default:
feState.topologyProvokingVertex = 0;
}
feState.bEnableCutIndex = info->primitive_restart;
ctx->api.pfnSwrSetFrontendState(ctx->swrContext, &feState);
if (info->index_size)
ctx->api.pfnSwrDrawIndexedInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->index_bias,
info->start_instance);
else
ctx->api.pfnSwrDrawInstanced(ctx->swrContext,
swr_convert_prim_topology(info->mode),
info->count,
info->instance_count,
info->start,
info->start_instance);
/* On large client-buffer draw, we used client buffer directly, without
* copy. Block until draw is finished.
* VMD is an example application that benefits from this. */
if (ctx->dirty & SWR_LARGE_CLIENT_DRAW) {
struct swr_screen *screen = swr_screen(pipe->screen);
swr_fence_submit(ctx, screen->flush_fence);
swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
}
}
